Dry etch post process method
一种干蚀刻、处理室的技术,应用在半导体制造工艺领域,能够解决产品电连接错误、良率低、难以完全去除聚合物等问题,达到提高产品良率、避免电连接错误的效果
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[0014] Please refer to FIG. 4 to FIG. 8 , which are schematic diagrams of dry etching to form the source and drain layers (Source electrode & Drain electrode, SD) of the thin film transistor. Please refer to FIG. 4 , which is a deposition step, depositing an SD metal layer 50 on the glass substrate 10 , and then depositing a passivation layer 40 on the SD metal layer 50 and the substrate 10 . Please refer to FIG. 5 , which is a photomask manufacturing process. Photoresist is coated on the passivation layer 40 , and then exposed through a photomask to form a photoresist layer 30 with openings. Please refer to Fig. 6, it is a dry etching step, using O in a dry etching chamber (not shown). 2 , SF 6 and CF 4 The gas etches a portion of the passivation layer 40 to form a contact hole 70, during which a polymer layer 60 is formed and covers the contact hole 70 and the like. Please refer to Figure 7 for post-dry etch processing steps using SF 6 Ashing is performed to remove the p...
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