'Soft error suppress circuit based on isolate method

A technology for suppressing circuits and soft errors, applied in information storage, static memory, digital memory information, etc., can solve the problem of "soft error" suppression effect is small

Inactive Publication Date: 2009-03-18
TSINGHUA UNIV
View PDF3 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In this approach, the transmission gate is always on, and the suppression effect on "soft errors" is relatively small

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • 'Soft error suppress circuit based on isolate method
  • 'Soft error suppress circuit based on isolate method
  • 'Soft error suppress circuit based on isolate method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0030]The circuit of the present invention can be slightly improved and obtained from the existing SRAM unit circuit: two transmission gate units are added, wherein, the grid of the NMOS transistor of the transmission gate is connected to the control line of the Bit line; and the grid of the PMOS transistor is grounded, Leave it normally open. In addition, there is no need to make any changes to the original circuit.

[0031] When this circuit is applied in a SRAM cell, it is shown in the figure. The work of the circuit is divided into two states: access state (AccessState) and hold state (Keep State), such as figure 1 shown. In the access state, the control signal makes the transmission gate turn on, and the data is stored or read normally; in the hold state, the NMOS transistor of the transmission gate is turned off, and the PMOS transistor is turned on. sub-hit, which is equivalent to connecting an inrush current source at point A(C), such as figure 2 shown. The inst...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The "soft error" suppression circuit based on the isolation method belongs to the field of high reliability integrated circuit design. It is characterized in that the sensitive nodes in the circuit are isolated with controllable transmission gates, thereby isolating the "soft error" transmission path, effectively The occurrence of "soft errors" is suppressed. Thus reducing the likelihood of "soft errors" occurring.

Description

technical field [0001] The application field of "'Soft Error' Suppression Circuit Structure Based on Isolation Method" is the design of high-reliability large-scale integrated circuits. The proposed circuit is suitable for integrated circuits that need to work in strong radiation areas. It can greatly suppress the instantaneous current generated when neutrons, alpha particles, cosmic rays and other radiation sources irradiate the CMOS transistor channel at the cost of relatively small power consumption and area. So as to achieve the purpose of suppressing "soft errors". Background technique [0002] As the feature size of the CMOS process has entered 100 nanometers, the number of transistors integrated on a chip is increasing, and at the same time, more and more storage resources such as SRAM and cache memory are integrated on the chip. At this time, the probability of "soft errors" in the circuit is also increasing. [0003] "Soft Errors" (Soft Errors) is a temporary abn...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/412G11C11/417
Inventor 罗嵘何苦陈亦波杨华中
Owner TSINGHUA UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap