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Data by-passage technology in digital signal processor

A digital signal, bypass system technology, applied in machine execution devices, concurrent instruction execution, etc., can solve the problems of not getting results, stalling and waiting, and achieve the effects of reducing conflict stalls, increasing clocks, and reducing delays

Inactive Publication Date: 2009-07-15
ZHEJIANG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, the pipeline must stall and wait until the ARm value is written, and its value is bypassed to the ID stage, otherwise the expected result will not be obtained

Method used

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  • Data by-passage technology in digital signal processor
  • Data by-passage technology in digital signal processor
  • Data by-passage technology in digital signal processor

Examples

Experimental program
Comparison scheme
Effect test

example 1

[0061] Example 1, consider the following 2 instructions:

[0062] ADD A, B, C

[0063] SUB D, A, E

[0064] The first instruction performs the operation of B+C and stores the result in register A. The second instruction performs the A-E operation and stores the result in register D. Since the source register A of the second instruction uses the calculation result of the first instruction, there is a data dependency between the two instructions. Therefore, when the second instruction is at the decoding stage, the control unit will judge the data conflict control information S35, so that the pipeline IF and ID will stop, while other stages continue to execute. Until the first instruction is executed to the WB level, the parallel data conflict detection in the data bypass circuit compares the address value, the comparator CMP5 will find that the read address and the write address are the same, both are A registers, and the output cc5 of the comparator CMP5 will change to Comp...

example 2

[0065] Example 2, consider the following 3 instructions:

[0066] ADD ARm, B, C

[0067] SUB D, *ARm++(IR0), *ARn++(IR1)

[0068] ADD E, *ARm+(4), F

[0069] The first instruction is an addition instruction, which realizes B+C, and the result is stored in the address register ARm. The second instruction is more complicated, and it implements a subtraction operation. The two operands come from the memory numbers whose addresses are ARm+IR0 and ARn+IR1. At the same time, the value of the ARm register will be updated to the value of ARm+IR0, and the value of the ARn register will be updated to the value of ARn+IR1. The result of the subtraction is stored in register D. The third instruction is still an addition instruction. The two operands come from the memory number, the memory address is the result of ARm+4, and the other operand comes from the register F. In this example, there is a data correlation between the ARm of the first instruction and the second instruction, and...

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Abstract

The invention discloses a microprocessor and a computer system, and aims to provide a memory-oriented digital signal processor (DSP) structure, and particularly relates to the data bypass technology in the digital signal processor. The present invention proposes a new data bypass technology. In this circuit, 6 channels of data forwarding are realized, of which 4 channels perform priority parallel data selection for 11 data sources, and 2 channels perform parallel data selection for 3 data sources. Perform prioritized parallel data selection. The beneficial effect of the invention is to reduce the conflict pause in the assembly line, reduce the time delay, increase the clock of the processor, thereby improving the real-time processing ability. The data bypass technology in the digital signal processor of the 6-stage pipeline structure that the present invention designs has all adopted parallel processing technology to key 4 roads, and general practice is that each road needs to carry out serial data selection with 10 data selectors .

Description

technical field [0001] The present invention relates to a microprocessor and a computer system. More specifically, the present invention relates to a memory-oriented digital signal processor (DSP) structure, and in particular to a data bypass system applied in a digital signal processor assembly line. Background technique [0002] With the development of modern microelectronics technology and the increase in demand in practical applications, digital signal devices for memory operations are becoming more and more popular. The biggest feature is that two data can be taken out from the on-chip data memory at the same time within one clock. Logic, Calculation and other operations. Due to the trend of personalization and customization of electronic equipment, digital signal processors must pursue higher and faster computing speeds. Under certain process conditions, the use of multi-stage pipeline structure has become a means to solve clock bottlenecks. Now take the 6-stage pipel...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/38
Inventor 陈晓毅刘鹏姚庆栋李东晓俞国军
Owner ZHEJIANG UNIV
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