Pulsed D-flip-flop using differential cascode switch

Abstract

A differential cascode structure is configured to propagate a data state to a static latch at each active edge of a clock. A clock generator enables the communication of the data state and its inverse to the latch for a predetermined time interval. In a first embodiment, each cascode structure includes three gates in series, the gates being controlled by the clock signal, a delayed inversion of the clock signal, and the data state or its inverse. In an alternative embodiment, each cascode structure includes two gates in series, the gates being controlled by the clock signal and the delayed inversion of the clock signal. In this alternative embodiment, each of these cascode structures is driven directly by the data signal or its inverse. The static latch obviates the need to precharge nodes within the device, thereby minimizing the power consumed by the device. The latch preferably comprises cross-coupled inverters, which, being driven by the differential cascode structure, enhance the switching speed.

Description

technical field [0001] The present invention relates to the field of electronic circuit design, and in particular to a pulse-triggered D-type flip-flop (P-DFF), which utilizes cascaded voltage switches to achieve minimum settling time and propagation delay while having minimum power consumption. Background technique [0002] The data flip-flop (DFF) is set up to "read in" the data input at a specific point each clock cycle. The output of the DFF maintains the value read in, regardless of any subsequent changes, or noise, on the data input until the next data value is read in. The data input must be stable while being read into the DFF, otherwise the read value may be indeterminate. Under ideal conditions, the reading of the data input occurs instantaneously to minimize the sensitivity of the DFF to changes in the data input. Also, ideally, instantaneous reads occur at exactly the same point in each clock cycle. [0003] Pulse-triggered latches and flip-flops are commonly ...

AI Technical Summary

Problems solved by technology

In fact, device 210 is a self-regulating device that automatically limits the sensitivity of the SDFF to either the preset delay associated with device 210, or the actual time required to propagate the data input to the internal nodes, whichever is shorter

Images