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High-frequency integrated circuit package structure with unification projection jointing altitude and method for manufacturing the same

A technology of integrated circuits and packaging methods, applied in the direction of circuits, semiconductor/solid-state device manufacturing, electrical components, etc., to achieve the effect of product structure improvement and wide utilization of value

Inactive Publication Date: 2009-09-09
CHIPMOS TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The main purpose of the present invention is to overcome the defects of the existing integrated circuit packaging structure and provide a new type of integrated circuit packaging structure. Flip-chip bonding can reduce the complexity of the process and increase the speed of mass production, and has the functions of short electrical conduction path, preventing punching and thinning the package, so it is more suitable for practical use

Method used

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  • High-frequency integrated circuit package structure with unification projection jointing altitude and method for manufacturing the same
  • High-frequency integrated circuit package structure with unification projection jointing altitude and method for manufacturing the same
  • High-frequency integrated circuit package structure with unification projection jointing altitude and method for manufacturing the same

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Embodiment Construction

[0058] In order to further explain the technical means and effects that the present invention adopts to achieve the predetermined invention purpose, the following in conjunction with the accompanying drawings and preferred embodiments, the high frequency integrated circuit packaging structure and its The specific implementation, structure, features and effects of the manufacturing method are described in detail below.

[0059] see figure 2 , in the first embodiment of the present invention, a high-frequency integrated circuit packaging structure 200 with uniform bump bonding height mainly includes a substrate 210, a multi-stage die-bonding layer 220, a chip 230 and a plurality of external terminals 240.

[0060] The substrate 210 has a first surface 211 and a second surface 212 , wherein a plurality of bump pads 213 are formed on the first surface 211 . The substrate 210 can be a printed circuit board or a circuit film. Preferably, the substrate 210 is a circuit film such ...

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Abstract

The invention relates to a packaging structure of high frequency integrated circuits for uniformizing adjoining heights of projections and a manufacturing method. The packaging structure of the high frequency integrated circuits mainly comprises a base plate, a multi-stage die bond layer, a projecting wafer and a plurality of external terminals. The multi-stage die bond layer is formed on the base plate to bond the active surface of the wafer. Pluralities of projections are disposed on the active surface. When the projections are linked to the projection joint of the base, the multi-stage die bond layer bonds the active surface of the wafer simultaneously. Therefore, the adjoining heights of the projections can be in unification, the projections are arranged on a crystal pad originally or are in non-matrix arrangement, thereby without re-arranging circuit layers, and the invention can provide relatively transmission paths of short electric property to suit low-cost high frequency integrated circuit package.

Description

technical field [0001] The invention relates to a high-frequency integrated circuit packaging technology, in particular to a high-frequency integrated circuit packaging structure with uniform bump bonding height and a manufacturing method thereof. Background technique [0002] Integrated circuit packaging technology hopes to protect higher-frequency, faster-computing integrated circuit chips with a more simplified manufacturing process and lower packaging costs. However, the current packaging method uses wire bonding or flip-chip bonding technology for the electrical connection between the chip and the substrate. The wire bonding has an electrical transmission distance and cannot be used for high-frequency integrated circuits. Flip-chip bonding requires A redistribution layer (RDL) is formed on the surface of the flip chip so that the bumps required by the flip chip are arranged in a matrix, but the cost is high, especially not suitable for memory packages with lower pins. ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/488H01L23/31H01L21/60H01L21/56
CPCH01L2924/15311H01L2224/48091H01L2224/83192H01L2224/73215H01L2224/16225H01L2224/73204H01L2224/32225H01L2224/4824H01L2924/00014H01L2924/00
Inventor 刘光华
Owner CHIPMOS TECH INC