Mistake recovery in integrated circuit processing level
An integrated circuit and error technology, which is applied in the direction of data error detection, error detection/correction, etc., in the direction of data redundancy in electrical digital data processing and calculation, and can solve problems such as the difficulty in ensuring that the sequential logic of the pipeline is free from operational errors.
Active Publication Date: 2009-12-02
ARM LTD +1
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Problems solved by technology
Furthermore, in the embodiment of US-2004-0199821, the existing pipeline timing logic is used to achieve error recovery by reading the data value from the delayed latch, but it may be difficult to ensure that the pipeline timing logic itself does not operate The effect of errors, either directly due to the critical path in the control logic itself or indirectly by feeding metastable values from the data path to the control logic
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[0045] figure 1 The diagram illustrates a portion of an integrated circuit, which may be part of a synchronous pipeline in a processor core (eg, an ARM processor core designed by ARM Limited, Cambridge, UK). A synchronous pipeline is formed by a number of processing stages, the first stage comprising logic blocks 3010 followed by latches 3020 in the form of flip-flops. The output of the logic block 3010 is provided to a transition detector 3030, which can be used to detect transitions in logic signal values that occur within predetermined time windows and indicate errors in the operation of the integrated circuit. Such an error in operation may occur if the operating parameters applicable to the integrated circuit are such that the logic module 3010 cannot complete its processing operation before the flip-flop 3020 captures its value.
[0046] The operating parameters of the integrated circuit include the frequency of the clock signal provided by the clock 3031 , the operat...
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An integrated circuit includes error detection circuits 3230-1 to 3230-4 that are capable of detecting transitions in signal values within a predetermined time window that indicate errors in the operation of the integrated circuit. The integrated circuit also includes a storage unit 3296 capable of storing a resumed state of the data processing arrangement comprising at least a subset of structural state variables corresponding to a programmer mode of the integrated circuit. Error recovery circuits 3250 , 3260 , 3210 are provided as part of the integrated circuit and are used to enable the integrated circuit to recover from detected operational errors using recovery states stored in memory unit 3296 . Integrated circuit operating parameter controller 3242 adjusts integrated circuit operating parameters, such as clock frequency, operating voltage, substrate bias voltage, temperature, based on one or more characteristics of detected errors in operation, to adopt improved overall performance in a way to maintain a bounded non-zero error rate.
Description
technical field [0001] The invention relates to the field of integrated circuits. More particularly, the present invention relates to detecting and recovering from operational errors at the processing level of integrated circuits. Background technique [0002] Methods of providing integrated circuits connecting processing stages, such as pipeline circuits, in series are well known. Each processing stage includes processing logic and latches, wherein the latches are used to store the output values of each stage to provide as input to subsequent processing stages. The time that processing logic takes to complete its processing operations depends on the speed at which the integrated circuit operates. The fastest rate at which processing logic can operate is limited by the slowest level of processing logic. To be able to process data as fast as possible, the processing stages of a circuit are driven as fast as possible until the slowest processing stage can't keep up. Howe...
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IPC IPC(8): G06F11/14
CPCG06F11/1407
Inventor D·T·布劳夫D·M·布尔S·达斯
Owner ARM LTD