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Chip package structure, chip carrier tape and its planarization method

A chip packaging structure and carrier tape technology, which is applied to electrical components, electrical solid devices, circuits, etc., can solve the problems that the chip 17 cannot be properly joined to the chip carrier tape 10, the alignment is difficult, and it is unpleasant to see.

Inactive Publication Date: 2009-12-23
CHIPMOS TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, since the chip carrier tape 10 itself is a composite structure made of different materials, which not only belongs to soft materials, but also has different thermal expansion coefficients between different materials in each layer, after various temperature changes in the process (for example, in the process of Baking, heat treatment), different materials produce different degrees of expansion and contraction, and the flatness of the chip carrier tape 10 is affected; in addition, the chip carrier tape 10 is usually stored in the form of a roll after production, which may also cause internal stress Cumulatively, once the chip carrier tape 10 is cut, the warpage will be more obvious due to the lack of restraint to the internal stress; all the above factors may make the chip carrier tape 10 and the chip 17 bonded before or after bonding. warpage
[0004] The above-mentioned warping phenomenon is not conducive to the tape and reel packaging process. For example, if the chip carrier tape 10 has a warped and uneven shape, the positioning of the chip carrier tape 10 and the chip 17 will be inaccurate during the manufacturing process, so that the chip 17 cannot correctly bonded to the preset position on the chip carrier tape 10; in addition, if the chip carrier tape 10 with the chip 17 has been installed with a warping phenomenon, it is not conducive to the subsequent application of the chip carrier tape 10, such as with the external When components (such as circuit boards, glass substrates, etc.) are wire bonded, problems such as alignment difficulties, empty soldering, or insufficient soldering strength will occur due to warpage, which will affect the reliability of the product

Method used

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  • Chip package structure, chip carrier tape and its planarization method
  • Chip package structure, chip carrier tape and its planarization method
  • Chip package structure, chip carrier tape and its planarization method

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Embodiment Construction

[0034] First of all, please refer to the first embodiment of the present invention figure 2 , shows a schematic cross-sectional view of the chip carrier tape 20 , the chip carrier tape 20 includes a flexible substrate layer 21 , a wire layer 23 and a solder resist layer 25 . In order to clearly disclose the present invention, the flexible substrate layer 21 can be divided into a first region 211, a second region 212 and a third region 213, wherein the wiring layer 23 is formed on the flexible substrate layer 21, and extend from the second area 212 into the first area 211 and the third area 213 respectively, while the solder resist layer 25 is formed on the flexible substrate layer 21, and covers the wire layer 23 on the second area 212 .

[0035] The feature of this embodiment is that a part of the chip carrier tape 20 on the second region 212 has an indentation profile 31 . As shown in the figure, in the second area 212, the thickness of the area where the embossed outline...

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Abstract

The invention relates to a chip package structure, and a chip carrier tape and a planarization method thereof. Molding is performed on a local area of the chip carrier tape to form a stamping profile which is used for correcting warping phenomenon of the chip carrier tape, thus causing the chip carrier tape to be planar.

Description

technical field [0001] The invention relates to a chip packaging structure, a chip carrying tape and a flattening method thereof; in particular, a chip packing structure, a chip carrying tape and a flattening method for improving warpage by forming an embossed contour. Background technique [0002] With the advancement of industry, semiconductor components (such as chips) have become one of the indispensable components in many products. After the chip is manufactured, subsequent packaging operations are required to protect the internal circuit and electrically connect with other external components. With the evolution of packaging technology, chip packaging methods are also increasingly improved and diversified. One of the common packaging methods is Tape Automatic Bonding (TAB). Tape automatic bonding packaging technology can be further divided into tape carrier package (Tape Carrier Package, TCP) and film-on-chip packaging (Chip-On-Film, COF), both of which bond the chip ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/498H01L21/60H01L21/48
CPCH01L2224/92125H01L2224/73204H01L2224/16225H01L2224/32225
Inventor 陈崇龙赖奎佑
Owner CHIPMOS TECH INC