Chip package structure, chip carrier tape and its planarization method
A chip packaging structure and carrier tape technology, which is applied to electrical components, electrical solid devices, circuits, etc., can solve the problems that the chip 17 cannot be properly joined to the chip carrier tape 10, the alignment is difficult, and it is unpleasant to see.
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[0034] First of all, please refer to the first embodiment of the present invention figure 2 , shows a schematic cross-sectional view of the chip carrier tape 20 , the chip carrier tape 20 includes a flexible substrate layer 21 , a wire layer 23 and a solder resist layer 25 . In order to clearly disclose the present invention, the flexible substrate layer 21 can be divided into a first region 211, a second region 212 and a third region 213, wherein the wiring layer 23 is formed on the flexible substrate layer 21, and extend from the second area 212 into the first area 211 and the third area 213 respectively, while the solder resist layer 25 is formed on the flexible substrate layer 21, and covers the wire layer 23 on the second area 212 .
[0035] The feature of this embodiment is that a part of the chip carrier tape 20 on the second region 212 has an indentation profile 31 . As shown in the figure, in the second area 212, the thickness of the area where the embossed outline...
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