Clock and data recovery circuit

Abstract

There is provided a clock data reproduction circuit capable of improving the following speed following the reception data signal fluctuation and the clock quality as well as automatically performing adjustment to an optimal identification phase. The clock data reproduction circuit includes: a first feedback loop (204) having a phase comparator (209) for inputting clock from a VCO (203) and a reception data signal and detecting a phase difference, an integration circuit (210), and the VCO (203); and a second feedback loop (207) having an identifier (205) for inputting a reception data signal (201), a phase comparator (211) for inputting the output from the identifier (205) and the reception data signal (201) and detecting a phase difference, an integration circuit (212), and a phase shifter (208) for inputting the clock outputted from the VCO (203), shifting the phase according to the integration output of the integration circuit (212) when outputting it.

Description

Technical field [0001] The present invention relates to a clock data regeneration circuit that regenerates a clock for identification by using a data signal to identify / regenerate an input data signal. Background technique [0002] Hereinafter, such a conventional clock data reproduction circuit will be described. Figure 8 It is a diagram showing the structure of a clock data reproduction circuit disclosed in Non-Patent Document 1 described later. If refer to Figure 8 , The clock data regeneration circuit includes: a phase comparator (Phase Detector) 602 that compares the phases of the two input signals and outputs the comparison result; an integration circuit 603 that integrates the phase comparison result signal; based on the output from the integration circuit 603 A voltage controlled oscillator (Voltage Controlled Oscillator: abbreviated as “VCO”) 604 whose oscillation frequency is variable by voltage constitutes a feedback loop (feedback loop) 601. The integrating circuit 6...

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Problems solved by technology

[0021] However, in the above constitution, there are the following problems: as Figure 12 As shown in (a), since the response time of the output of the integrating circuit (VCO control signal) to data fluctuations becomes longer, as shown in Figure 12 As shown in (b), the clock data regeneration circuit cannot immediately track the instability or fluctuation of the transmission data signal, so the time until the correct clock is output again and the data regeneration becomes longer

[0022] On the other hand, in the case of reducing the time constant of the integrating circuit in order to shorten the response time, there is a problem that if Figure 12 As shown in (c), the amount of fluctuation of the clock control voltage increases when the signal is continuous with the same sign, and the synchronization of the clock is deviated or the phase noise is increased.

Usually, this delay time greatly affects the transmission data rate or the circuit configuration, so it is difficult to set the optimum circuit constants

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