Testing method capable of configuring FPGA configurable logic block with five times

Abstract

The present invention provides a testing method of the FPGA configurable logical blocks completed after five times of configuring. The characteristics reside in that: the testing is performed by combining the sequential logical circuit and the combinational logic circuit of the FPGA configurable logical blocks, and the testing times of the configuration can be reduced by optimizing the arrangement of the testing resources and using the and, or, etc. function and the testing vectors of the exhaustive attack method alternately; in the present invention, a technology of the concatenated snake-shaped one dimensional array is used, and all the configurable logical blocks to be tested are connected in series according the demand of the controllability testing and the observability testing and are then tested. Thus, the design is simplified, and the input and output ports of the testing are reduced, and a 100% testing coverage rate is achieved, and the testing cost is reduced effectively.

Description

technical field [0001] The invention relates to a test method of an FPGA chip, in particular to a test method for completing FPGA configurable logic blocks with only five configurations. Background technique [0002] The premise of testing the FPGA is to configure it, design a variety of test circuits and go through multiple configuration-test processes to achieve effective testing of the FPGA. It takes much more time to configure an FPGA than to apply a test vector, so the key to improving the efficiency of FPGA testing is to minimize the number of configurations while ensuring test coverage. [0003] The configurable logic block is the most basic functional unit in the FPGA, and the comprehensive test of the configurable logic block is in a very important position in the FPGA testing technology. At present, foreign countries have conducted research on the testing of FPGA configurable logic blocks, and proposed the theory that the configurable logic blocks are divided into...

AI Technical Summary

Problems solved by technology

[0004] The problem solved by the present invention is to reduce the number of configurations as much as possible, and provide a method for testing FPGA configurable logic blocks through five configurations. It guarantees the requirements of test controllability and test observability, and overcomes the shortcomings of many test configurations, complex test circuit structure and low efficiency in the past

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