Semiconductor storage device

Abstract

A semiconductor storage device comprises a memory cell array having memory cells arranged in a matrix, each memory cell mainly composed of a flip-flop formed of a pair of cross-coupled inverters, a first wiring configured to each row and each column of the memory cell array and connected to a predetermined power supply node, a second wiring configured in parallel to the first wiring, and a switching circuit that is connected between the power supply node and the second wiring and opens when initial data is set to the memory cells, wherein a receiving node of each pair of inverters is selectively connected to the first wiring or the second wiring in accordance with a logical value of initial data to be set to each one of the plurality of the memory cells belonging to each row and each column of the memory cell array.

Description

[0001] Cross References to Related Applications [0002] This application is based on Japanese Patent Application No. 2006-098035 filed on March 31, 2006, the entire contents of which are incorporated herein by reference. technical field [0003] The present invention relates to a semiconductor memory device, and more particularly, to a Static Random Access Memory (SRAM) capable of automatically setting initial data to memory cells. Background technique [0004] Generally, a static random access memory (SRAM) that can set predetermined initial data to a memory cell is known (refer to Japanese Laid-Open Patent No. 2005-85399). [0005] FIG. 9 shows the structure of a memory cell 1000 equipped to that kind of SRAM. The memory cell 1000 is composed of a flip flop formed by a pair of cross-coupled inverters 1001 and 1002, a transmission gate formed by transistors 1004 and 1006, and a transistor 1010 for setting initial data. Also, each of the inverters 1001 and 1002 is constit...

AI Technical Summary

Problems solved by technology

[0007] According to the prior art described above, since each memory cell constituting the memory cell array has a transistor 1010 for setting initial data, a large number of transistors constitute the memory cell, so that the degree of integration will be significantly reduced.

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