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Multi-memory module circuit and method for reducing resistance incontinuity

A memory module, multi-memory technology, applied in static memory, digital memory information, information storage and other directions

Active Publication Date: 2012-07-25
INT BUSINESS MASCH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Operating a memory subsystem implementing a two-DIMM layout or a four-DIMM layout at higher speeds can cause memory subsystem data errors due to signal reflections or intersymbol interference

Method used

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  • Multi-memory module circuit and method for reducing resistance incontinuity
  • Multi-memory module circuit and method for reducing resistance incontinuity
  • Multi-memory module circuit and method for reducing resistance incontinuity

Examples

Experimental program
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Embodiment Construction

[0017] from figure 1 Initially, an exemplary multiple memory module circuit topology according to an embodiment of the present invention is described with reference to the accompanying drawings. figure 1 A line drawing illustrating an exemplary multiple memory module circuit layout according to an embodiment of the invention is set forth. figure 1 An exemplary multiple memory module circuit topology in includes: a memory controller (102); a plurality of memory modules (106, 108) connected to the memory controller (102) by a memory bus (104); and connected in a star topology A resonator (100) to the plurality of memory modules (106, 108). figure 1 The exemplary multiple memory module circuit topology advantageously operates to reduce figure 1 Impedance discontinuities in the multi-memory module circuit depicted in . Impedance discontinuities exist at boundaries between media with different impedances. When an electrical signal in a circuit encounters an impedance disco...

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PUM

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Abstract

A multi-memory module circuit topology is disclosed that includes a memory controller, a plurality of memory modules connected to the memory controller through a memory bus, and a resonator connected to the plurality of memory modules in a starburst topology. A method for reducing impedance discontinuities in a multi-memory module circuit is disclosed that includes providing a plurality of memorymodules connected to a memory controller through a memory bus, selecting a starburst topology, and connecting a resonator to the plurality of memory module in dependence upon the selected starburst topology. An additional method for reducing impedance discontinuities in a multi-memory module circuit is disclosed that includes providing by a resonator a predetermined discontinuity reducing impedance at a predetermined location in the multi-memory module circuit between at least two memory modules, the multi-memory module circuit having a plurality of components of logically arranged around thepredetermined location.

Description

technical field [0001] The field of the invention is multiple memory module circuit topologies. Background technique [0002] The development of the EDVAC computer system in 1948 is often referred to as the beginning of the computer age. Since then, computer systems have evolved into extremely complex devices. Today's computers are far more complex than early systems such as the EDVAC. A computer system typically includes a combination of hardware and software elements, application programs, operating system, processors, buses, memory, input / output devices, and the like. Advances in semiconductor processing and computer architecture have been used to drive the performance of computers ever higher and have made today's computer systems far more powerful than those of just a few years ago. [0003] Among advances in semiconductor processing and computer architecture, advances in computer memory subsystems have played an important role in creating more powerful computers. ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C5/02G11C7/10
CPCG11C5/04G11C5/063
Inventor M·凯斯D·N·德阿奥乔E·马托格卢P·帕特尔N·H·法姆
Owner INT BUSINESS MASCH CORP
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