Unlock instant, AI-driven research and patent intelligence for your innovation.

Semiconductor chip package and its packaging method

A chip package, packaging method technology, applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device parts and other directions

Inactive Publication Date: 2007-10-31
沈育浓
View PDF1 Cites 1 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the method disclosed in the above-mentioned U.S. patent needs to use a substrate to mount the semiconductor chip. Therefore, different semiconductor chips require different substrates in terms of size or function. Therefore, in terms of cost and There is a need for improvement in the packaging procedure

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Semiconductor chip package and its packaging method
  • Semiconductor chip package and its packaging method
  • Semiconductor chip package and its packaging method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0149] Before the present invention is described in detail, it should be noted that like elements are designated by like numerals throughout the specification.

[0150] 1 to 10 show a first preferred embodiment of the semiconductor chip package packaging method of the present invention.

[0151] Referring to FIG. 1 and shown in FIG. 45, a semiconductor wafer 1 is provided first. The semiconductor wafer 1 has a pad mounting surface 10 and a plurality of pads 11 mounted on the pad mounting surface 10 (in the drawing, only one pad 11 is shown).

[0152] It should be noted that the semiconductor wafer 1 shown in FIG. 1 may be a single wafer that has been cut from the wafer, but may also be a wafer that has not been cut from the wafer.

[0153] Next, as shown in FIG. 2 , an electroplating layer 2 is formed on each pad 11 of the chip 1 . The electroplating layer 2 slightly extends onto the pad mounting surface 10 of the wafer 1 .

[0154] Referring now to FIGS. 3 and 4 , a conduc...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A semiconductor wafer encapsulation and method are disclosed, the semiconductor wafer encapsulation includes: a semiconductor wafer which possesses a solder cushion mounting surface and several solder cushions which are mounted on the solder cushion mounting surface; several conductors, each of which possesses a extension part which is on the solder cushion mounting surface and extends as the track of circuit and a conducting connection part which is extended to a corresponding solder cushion; a protection layer which is formed on the whole solder cushion mounting surface of wafer to cover the conductor, several through holes which are connected with corresponding conductor are formed on the protection layer. The semiconductor wafer encapsulation and method in the invention possesses advantages that the encapsulation is simple, the column is small, and the cost is low.

Description

[0001] This application is a divisional application of an invention patent application with an application date of March 2, 2004, an application number of 200410007387.X, and an invention title of "semiconductor chip package and its packaging method". [technical field] [0002] The invention relates to a semiconductor chip package body and a package method thereof. [Background technique] [0003] In the early days, most of the packaging methods of semiconductor chips used lead frames as the medium for the electrical connection between the internal circuit of the chip and the external circuit. However, the integrated circuit packaged in this way is larger in size, and the transmission speed of the signal will be slower. Later, the ball grid array (BGA) packaging method appeared. As disclosed in US Patent No. 5,384,689. The integrated circuit packaged by the BGA packaging method is smaller in size, and the transmission speed of the signal will be faster. However, the method...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L23/485H01L23/488H01L21/60
CPCH01L2924/0002H01L2224/13
Inventor 沈育浓
Owner 沈育浓