Method and structure for reliable data copy operation for non-volatile memories

A non-volatile, memory system technology used in the field of Flash Electrically Erasable Programmable Read-Only Memory that solves the problem of not providing error checking and correction

Inactive Publication Date: 2007-11-07
SANDISK TECH LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, this known technique does not provide error checking and correction, but simply assumes that the data read from the first flash location is accurate

Method used

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  • Method and structure for reliable data copy operation for non-volatile memories
  • Method and structure for reliable data copy operation for non-volatile memories
  • Method and structure for reliable data copy operation for non-volatile memories

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Embodiment Construction

[0050] Figure 5 is a block diagram illustrating a semiconductor non-volatile memory constructed in accordance with one embodiment of the present invention. The memory system shown includes two separately addressed memory arrays 400-0 and 400-N, each with associated circuitry for addressing a particular word line, sensing threshold values ​​for cells on that word line The voltage and the storage of the read data for later use are very similar to the previous introduction to Figure 2. The memory system also has write circuitry associated with each array for erasing a group of cells controlled by one or more word lines, or for writing cells along one of the word lines. Figure 5 shows a system with two separate arrays and their associated circuitry, and a separate controller circuit, but it should be understood that a system with any desired number of such arrays of non-volatile memory cells, As well as in a system including a controller circuit in the same semiconductor device i...

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Abstract

An improved flash EEPROM memory-based storage subsystem includes one or more flash memory arrays, each with a duplicity of data registers and a controller circuit. When data are read from a flash array into a data register, the data is copied to a second register so that, during the ensuing program operation into the same array, the data may be transferred to the controller for the purpose of checking the data validity. This creates an improved performance system that doesn't suffer data transfer latency during copy operations but that is able to guarantee the validity of the data involved in such operations.

Description

[0001] This application is a divisional application of the patent application with the application number 01814497.7, the international filing date is August 16, 2001, and the invention title is "Novel Method and Structure for Reliable Data Copy Operation in Non-Volatile Memory". technical field [0002] The invention relates to the field of semiconductor non-volatile memory architecture and its operating method, which has been applied to flash electrically erasable programmable read-only memory (EEPROM). Background technique [0003] A common application of flash EEPROM devices is as a mass data storage subsystem for electronic equipment. Such subsystems are typically implemented either as removable memory cards that can be plugged into multiple host systems, or as non-removable memory embedded within the host system. In both devices, the subsystem includes one or more flash memory devices and often includes a subsystem controller. [0004] Flash EEPROM devices consist of ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C16/06G06F12/16G06F12/00G06F12/06G11C16/02
CPCG11C16/102G11C16/105G11C16/10
Inventor 凯文·M.·康雷丹尼尔·C.·古特曼卡洛斯·J.·宫扎列兹
Owner SANDISK TECH LLC
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