Asynchrous AHB interconnection matrix interface device

Abstract

The invention discloses asynchronous AHB interconnect matrix interface devices. Including a number of AHB main device control module, a module AHB request for arbitration, at least from an AHB device control module; AHB Each module contains the main control device controller device. The first and second units asynchronous induction latches latch unit; period from AHB device control module contains the device controller, register; AHB referred to the main device to control module for asynchronous clock lock AHB main way of receiving an order from the device, its signal will be converted to AHB clock domain signal from the device and after docking with the AHB control modules from the device parameters and data asynchronous clock and data exchange. This invention enabled the AHB AHB from the devices and devices can be at different clock domains, AHB agreement correct signal transmission integrity and improve the speed of the system bus and operational efficiency.

Description

technical field [0001] The invention relates to an AHB bus device of the AMBA protocol, in particular to an asynchronous AHB interconnection matrix interface device for parallel operation of multiple processors. Background technique [0002] The AHB bus is a high-speed bus for many embedded processors (especially ARM) to transmit data at the system level. The AHB interconnection matrix is ​​a system bus interconnection structure proposed by ARM, as shown in Figure 1. Now Companies with this device include synopsys and LSILOGIC's AHB interconnection matrix. Its advantage is that the bus transfer efficiency is high, but when it is applied to a multi-processor bus system with different clock domains, there are two disadvantages. One is that each processor subsystem must be in the same clock domain, and the other is due to timing differences. Affects the system bus speed of the embedded processor. [0003] As shown in Fig. 2 and Fig. 3, it is the operating waveform diagram of ...

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Problems solved by technology

[0005] First, each AHB master device and each AHB slave device must be in the same clock domain, otherwise, the transmission of the AHB signal will be disordered;

[0006] Second, the control signals of each AHB master device must pass through the input stage (input stage), but these signals themselves must be selected through the MUX together with the output results of the input stage, and these control signals will eventually be conducted to the control of the AHB slave device end, which causes heavy loading of these signals

[0018] It can be seen from the above description that a large number of control signals must be transmitted, so that the AHB interconnection matrix technology cannot be applied in the high-speed multi-processor multi-clock domain bus system

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