Global compiler for controlling heterogeneous multiprocessor

一种多处理器、编译程序的技术，应用在编译程序领域，能够解决开发时间、有效性能不实用等问题

Inactive Publication Date: 2007-12-12
WASEDA UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, this method is effective in a system with a few PUs. However, in a system integrating tens to thousands of PUs in the future, especially when the PUs are HCMP with a heterogeneous structure, it will be difficult in terms of development time and effective performance. is impractical

Method used

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  • Global compiler for controlling heterogeneous multiprocessor
  • Global compiler for controlling heterogeneous multiprocessor
  • Global compiler for controlling heterogeneous multiprocessor

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Embodiment Construction

[0061] One embodiment of the present invention will be described below with reference to the drawings.

[0062]

[0063] As an embodiment of the present invention, first, the configuration of a heterogeneous multiprocessor system (hereinafter, HCMP) 1 to which the parallel compilation method provided in the present invention is applied will be described with reference to the block diagram of FIG. 1 . In HCMP1, a plurality of heterogeneous processor units (PU) and shared memory (CSM) are configured. Each of these PUs is connected to an interconnection network (LBUS). In addition, the respective SMs are connected to the LBUS. Each PU is connected to a power supply voltage / clock frequency control circuit that supplies a power supply voltage and an operating clock to various parts such as a processor core and a memory of each PU. In this embodiment, the type and number of PUs are composed of two general processing processors (CPU), one signal processing processor (DSP), and tw...

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Abstract

Performance of a heterogeneous multiprocessor is educed as much as possible within a short time without any awareness of parallelization matched with a configuration of the heterogeneous multiprocessor. In a heterogeneous multiprocessor system, tasks having parallelism are automatically extracted by a compiler, a portion to be efficiently processed by a dedicated processor is extracted from an input program being a processing target, and processing time is estimated. Thus, by arranging the tasks according to PU characteristics, scheduling for efficiently operating a plurality of PU's in parallel is carried out.

Description

technical field [0001] The present invention relates to a compiling method and a compiling program for generating an execution program capable of efficiently operating a plurality of processor units in a multiprocessor system including a plurality of heterogeneous processor units. Background technique [0002] Due to the miniaturization of elements through the advancement of semiconductor manufacturing technology, a huge number of transistors can be integrated. At the same time, the frequency of processors is also increasing, but due to the increase in power during operation and the increase in power during standby due to leakage currents, the increase in operating frequency along the way through conventional processors The bounds begin to appear on the performance gains that can be achieved by improving the logic and logic. On the other hand, digital consumer devices such as car navigation systems, mobile phones, and digital TVs are on the market that simultaneously proces...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/45G06F9/46
CPCG06F8/456G06F8/37G06F9/3836G06F9/4405
Inventor 笠原博德木村启二鹿野裕明
Owner WASEDA UNIV
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