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Dual port memory device with reduced coupling effect

A memory and storage unit technology, applied in static memory, digital memory information, information storage, etc., can solve problems such as coupling effect, increased noise of storage unit 100, and reduced operating speed

Inactive Publication Date: 2008-01-23
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

These closely spaced conductors create coupling capacitance that slows down the operation and increases the noise of the memory cell 100
As semiconductor process technology improves, tighter wire configurations cause more severe coupling effects

Method used

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  • Dual port memory device with reduced coupling effect
  • Dual port memory device with reduced coupling effect
  • Dual port memory device with reduced coupling effect

Examples

Experimental program
Comparison scheme
Effect test

Embodiment

[0033] FIG. 2A shows a layout structure 200 of the DP SRAM cell shown in FIG. 1 according to an embodiment of the present invention. Pull-up PMOS transistors 106 and 110 , pull-down NMOS transistors 108 and 112 , and side-gate transistors 118 , 120 , 122 and 124 are constructed on a semiconductor substrate (not shown in FIG. 2 ). The first port bit line BL1, the first port inverted bit line BLB1, the second port bit line BL2, the second port inverted bit line BLB2, the power line V cc with the complementary supply line V ss Constructed in a first metal layer above a semiconductor substrate. These wires may be connected to terminals of different transistors in the semiconductor substrate through one or more via contact regions (not shown in FIG. 2 ). Complementary power line V ss Located between the second port bit line BL2 and the second port inversion bit line BLB2, and another complementary power line V ss Located between the first port bit line BL1 and the first port in...

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PUM

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Abstract

A dual port SRAM cell includes at least one pair of cross-coupled inverters connected between a power line and complementary power line. A number of pass gate transistors connect the cross-coupled inverters to a first bit line, a first complementary bit line, a second bit line, and a second complementary bit line on a first metal layer in the memory device. A first word line is coupled to gates of the first and second pass gate transistors, located on a second metal layer in the memory device. A second word line is coupled to gates of the third and fourth pass gate transistors, located on a third metal layer in the memory device, wherein the first, second and third metal layers are at different levels.

Description

technical field [0001] The present invention relates to an integrated circuit design, in particular to a dual-port memory device with reduced coupling effect. Background technique [0002] 1 shows a circuit diagram of a dual-port Static Random Access Memory (SRAM) unit 100. SRAM is a memory device commonly used in electronic products, such as mobile phones, digital cameras, PDAs, and personal computers. The DP SRAM cell 100 includes two cross-connected inverters 102 and 104 . The inverter 102 is composed of a pull-up PMOS transistor 106 and a pull-down NMOS transistor 108 . The inverter 104 is composed of a pull-up PMOS transistor 110 and a pull-down NMOS transistor 112 . The sources of the pull-up PMOS transistors 106 and 110 pass through the voltage line V cc Connect to a voltage source. The sources of the pull-down NMOS transistors 108 and 112 pass through the complementary voltage line V ss Connect to ground or a complementary voltage source. The gate of the pull-u...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/11H01L23/522G11C11/41H10B10/00
CPCG11C11/412H01L2924/0002H01L2924/00
Inventor 廖忠志
Owner TAIWAN SEMICON MFG CO LTD