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Semiconductor integrated circuit and test method thereof

A technology of integrated circuits and semiconductors, applied in the field of semiconductor integrated circuits and their testing, which can solve the problems of long time and insufficient time shortening.

Inactive Publication Date: 2008-02-27
FUJITSU MICROELECTRONICS LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

When the number of chips to be tested simultaneously is increased in order to shorten the test time, there is a problem that the time spent on the operation of causing the latch in the chip to store the trim code TM becomes very large, resulting in that the shortened time cannot be sufficiently achieved. Effect

Method used

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  • Semiconductor integrated circuit and test method thereof
  • Semiconductor integrated circuit and test method thereof
  • Semiconductor integrated circuit and test method thereof

Examples

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Embodiment Construction

[0039] FIG. 13 is a diagram showing an example of the structure of a semiconductor wafer 1300 according to an embodiment of the present invention. For example, sixteen semiconductor memory chips, ie, a first semiconductor memory chip 1301 to a sixteenth semiconductor memory chip 1316 , are formed on the semiconductor wafer 1300 .

[0040] FIG. 14 is a diagram showing the first semiconductor memory chips 1301 to sixteenth semiconductor memory chips 1316 and a tester 1401 for inspecting the first semiconductor memory chips 1301 to sixteenth semiconductor memory chips 1316 . The tester 1401 outputs a write enable signal / WE, an output enable signal / OE, and address signals A0 to A22 which are common to the sixteen semiconductor memory chips 1301 to 1316 . In addition, the tester 1401 outputs an individual chip enable signal / CE and inputs and outputs individual data DQ for each of the sixteen semiconductor memory chips 1301 to 1316 . The tester 1401 can test sixteen semiconducto...

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Abstract

A semiconductor integrated circuit is provided which includes a laser fuse circuit made to store a first trimming code by a laser radiation, an electric fuse circuit made to store a second trimming code by a voltage application, and an adjusting circuit adjusting an electric potential level or a timing depending on the first or second trimming code.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit and a testing method thereof. Background technique [0002] FIG. 11 is a diagram showing a structural example of a semiconductor memory chip 121 . The semiconductor memory chip 121 includes a test mode signal generation circuit 122 , a laser fuse circuit 125 , an internal potential generation circuit 123 , and a memory core (memory cell array) 124 . The test mode signal generating circuit 122 includes a volatile memory, and outputs a trim code TM as a test mode signal in the volatile memory. The trim code TM is a signal for adjusting the level of the internal potential in the plus or minus direction. The laser fuse circuit 125 is a nonvolatile memory having a laser fuse, and outputs a trim code LF similarly to the test mode signal generating circuit 122 . The internal potential generation circuit 123 generates an internal potential according to the trim code TM or LF, and supplies the inter...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C17/18G11C29/44
CPCG11C29/028G11C29/02G11C29/021G11C17/143G11C17/16G11C17/18G11C29/14G11C29/36
Inventor 山口秀策
Owner FUJITSU MICROELECTRONICS LTD