Method of preparing semiconductor device grids

Abstract

The invention provides a manufacturing method for the grid of semiconductor device, which comprises forming dielectric layer on the semiconductor underlay; forming polycrystalline silicon layer on the said dielectric layer; forming stack layer and positioning the grid location on the said polycrystalline silicon layer; etching the said polycrystalline silicon layer and the mask layer to form grid; oxidizing the polymer adhered to the root of the said grid; eliminating oxidized polymer by welt process; eliminating the said mask layer. The invention can produce grid with good shape, which is especially applicable to grid making with characteristic dimension of line width under 65nm.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for manufacturing a metal oxide semiconductor (MOS) device gate. Background technique [0002] With the rapid development of semiconductor manufacturing technology, in order to achieve faster computing speed, larger data storage capacity and more functions of semiconductor devices, wafers are developing towards higher component density and high integration. The gate of semiconductor devices become thinner and shorter than ever. After the manufacturing process enters the 65nm process node, the minimum line width of the gate can reach 40nm. In this case, the manufacture of the gate plays a crucial role in the performance of the MOS device. [0003] Polysilicon is the preferred material for manufacturing gates, which has special heat resistance and high etching pattern accuracy. The manufacturing method of the gate first needs to form a layer of gate ...

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Problems solved by technology

[0004] However, in the above process, since most of the etching gas is fluorine-containing gas, during the etching process, the fluorine in the etching gas will react with organic substances such as photoresist and BARC to form an organic polymer (polymer), and along the gate The etch direction is deposited at the position where the gate bottom is in contact with the gate oxide layer 110, causing root defects (footing), as shown in Figure 3 at 160

The existence of such root defects will affect the characteristic dimension of the line width of the gate, especially in the case of a very small gate width of the 65nm technology node, even a polymer with a width of only 1nm will have an adverse effect on the characteristic dimension of the gate line width. Change the effective channel length of the gate and destroy the device performance

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