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1000M and 10/100/1000M interface self-adapted Ethernet bridge

A bridge, Ethernet technology, applied in the field of Ethernet transmission, can solve the problems of data loss, small internal cache capacity and high price

Inactive Publication Date: 2008-03-19
ZTE CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The switch chip can realize multiple rate conversion functions, but the switch chip is usually designed with multiple ports, and the price is relatively high. More importantly, the switch chip is difficult to control the burst traffic from the high-speed port to the low-speed port, mainly because The control of the internal memory of the switching chip is designed for multi-ports, and the method of multi-port shared buffer is adopted, and the capacity of the internal buffer is relatively small. If a large number of burst data packets are encountered, the buffer will overflow, causing data lost
In addition, many switching chips do not support jumbo frames, which also limits the application range of switching chips

Method used

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  • 1000M and 10/100/1000M interface self-adapted Ethernet bridge
  • 1000M and 10/100/1000M interface self-adapted Ethernet bridge

Examples

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Embodiment Construction

[0015] The structure diagram of the Ethernet bridge of the present invention is shown in Figure 1, which is composed of a gigabit interface chip, FPGA, RAM, MCU, gigabit PHY and its media interface.

[0016] The dedicated chip in Figure 1 generally does not use GMII or TBI interfaces at the same time, but the 8B / 10B codec is considered in the FPGA design for use in different applications.

[0017] The core of the whole design is the FPGA chip. In the gigabit to gigabit working mode, the gigabit physical layer chip adopts the GMII interface. Since the speed of the FPGA input and output ends is equal, the FPGA only needs to transparently transmit all services; when working from gigabit to ten / hundred megabit In mode, the Gigabit physical layer chip is connected to the FPGA through the MII interface. Since the speeds of the FPGA input and output ports are not equal, enough external buffers must be used to buffer burst traffic in the Gigabit direction. When the buffer usage exceed...

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PUM

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Abstract

The invention discloses an Ethernet Bridge connector with self-adaptive kilomega and ten / hundred / kilomega interface, which solves the inability to transform interfaces of various rates and the difficulty in controlling burst flow quantity from high speed port to low speed port. The Ethernet Bridge connector comprises a kilomega interface chip, a field programmable gate array, a field programmable gate array external hanging memory, a kilomega physical layer chip and a micro-controller small system, wherein the kilomega interface chip is connected with the field programmable gate array through a kilomega interface; the kilomega physical layer chip is connected with the field programmable gate array through a kilomega bit medium independent interface; the micro-controller controls the kilomega interface chip through a local bus and controls the kilomega physical layer chip through an MDIO interface. The invention has the advantages of low cost, flexible interface, automatic selection of a plurality of speed rates, sound buffering performance when interfaces at different rates are in bridge connection, with corresponding function of customization of different applications.

Description

technical field [0001] The invention belongs to the field of Ethernet transmission, in particular to an Ethernet bridge. Background technique [0002] In the process of designing and developing Ethernet transmission equipment, some special-purpose chips used usually only support Gigabit interfaces (GMII or TBI), but interfaces of different rates are required in different applications. A typical application It is a gigabit optical fiber transceiver: a remote device provides gigabit optical fiber, and the user end currently only supports ten / hundred megabit electrical interfaces. In order to protect user investment and upgrade capabilities, the user end is required to have the ability to interface with multiple rates. [0003] Using a switch chip can realize multiple rate conversion functions, but the switch chip is usually designed for multi-port, and the price is relatively high. More importantly, the switch chip is difficult to control the burst traffic from the high-speed ...

Claims

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Application Information

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IPC IPC(8): H04L29/10
Inventor 李岩陆建鑫王静璇
Owner ZTE CORP