Current generating apparatus and feedback-controlled system utilizing the current generating apparatus

Abstract

The present invention discloses a current generating apparatus for generating an output current. The current generating apparatus includes: a first current mirror; a first bias current generator for providing a first bias current, and the first bias current generator includes: a first current source for providing the first current; and a capacitive device for conducting a reference current; a second current mirror for generating a second mirror current; a second bias current generator for generating a second current; a third current source for providing a third current, wherein the second mirror current is equal to the third current; a feedback circuit; and a fourth current source for providing a fourth current, wherein the output current is outputted at an output node of the first current mirror.

Description

technical field [0001] The present invention relates to a frequency compensation mechanism, and more particularly to a feedback control system (such as a low-dropout voltage regulator) for frequency compensation using a current generating device that minimizes the DC offset in the output current. Background technique [0002] Please refer to FIG. 1 , which shows a first known low dropout voltage regulator 10 (Low dropout voltage regulator). The LDO regulator 10 includes a pass transistor MP, a feedback divider circuit 11 and an error amplifier 12 . The connection relationship between the transfer transistor MP, the feedback voltage divider circuit 11 and the error amplifier 12 is shown in FIG. 1, wherein the input terminal N of the low dropout regulator 10 in Connected to a power supply voltage VDD, the output terminal N of the low dropout voltage regulator 10 out connected to a load which is equivalent to a resistor R L Connect a capacitor C in parallel L To represent. ...

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Problems solved by technology

On the other hand, using the above zero point ω ESR to compensate the pole of the low-dropout regulator 10 has at least three disadvantages: First, due to the high-frequency bypass capacitor C gdpass in parallel with capacitor C L Instead, another pole is provided, where the pole is close to the capacitor C L The resulting zero point ω ESR , so the added pole further reduces the phase margin of the LDO 10; second, the capacitor C L The equivalent series resistance R on the ESR It is often difficult to estimate effectively, and it will change with temperature; third, although the increasingly popular ceramic capacitors have low resistance value R ESR , cheaper and more area-saving, but at low resistance values ​​R ESR It is difficult to obtain an appropriate zero point ω in the case of ESR

However, due to the mismatch of the current mirror ratio N between the current mirror circuit 54a and the current mirror circuit 54b, a direct current ΔI will be generated B flow to the feedback resistor R F1 , R F2 , so it will equivalently form a parallel connection with the feedback resistor R F1 and R F2 The mismatch resistor R mismatch (As shown in Figure 6), therefore, the mismatch resistance R generated by the mismatch between the current mirror circuit 54a and the current mirror circuit 54b mismatch will change the output voltage V out

Furthermore, when the output voltage V out When changing, the DC current ΔI B It will also change accordingly, and in order to reduce the DC current ΔI B The impact caused, the current mirror ratio N of the current mirror circuit 54a and the current mirror circuit 54b must be as small as possible, and the grounding capacitance C 1 The larger the capacitance value, the better. However, a larger capacitance value will relatively increase the manufacturing cost and chip area.

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