Suppressing update of a branch history register by loop-ending branches

Abstract

A compiler or assembler, comprising a compiler or assembler operative to generate instructions in response to program code; and a loop-ending branch instruction marking function operative to indicate conditional branch instructions that terminate code loops.

Description

technical field [0001] The present invention relates generally to the field of processors, and more particularly to a method of improving branch prediction by suppressing updates to branch history registers with loop-ending branch instructions. Background technique [0002] Microprocessors perform computing tasks in a wide variety of applications. There is almost always a need for improved processor performance to allow faster operation and / or increased functionality through software changes. In many embedded applications (eg, portable electronic devices), power saving is also a goal of processor design and implementation. [0003] Many modern processors use a pipeline architecture in which successive instructions (each having multiple execution steps) overlap in execution. To achieve improved performance, instructions should flow continuously through the pipeline. Any situation that causes an instruction to stall in the pipeline can adversely affect performance. Both pe...

AI Technical Summary

Problems solved by technology

Second, the branch predictor in BPT 102 will take longer to "train", increasing the amount of code that must be executed before BPT 102 can begin to provide accurate branch predictions

This wastes BPT 102 space, increases branch prediction training time, and increases the potential for confusion in BPT 102, all of which reduce prediction accuracy

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