Integration process for fabricating stressed transistor structure

Abstract

A process flow integration scheme employs one or more techniques to control stress in a semiconductor device formed thereby. In accordance with one embodiment, cumulative stress contributed by RTP of a nitride spacer and polysilicon gate, and subsequent deposition of a high stress etch stop layer, enhance strain and improve device performance. Germanium may be deposited or implanted into the gate structure in order to facilitate stress control.

Description

Background technique [0001] During the processing of a substrate to fabricate circuits or displays, the substrate is typically exposed to an excited process gas that deposits materials on it or etches materials on it. The chemical vapor deposition (CVD) process uses a process gas excited by a high frequency voltage or microwave energy to deposit material on the substrate, which can be a layer, a contact hole filling, or other selective deposition structures. The deposited layer can be etched or otherwise processed to form active or passive devices on the substrate, such as metal-oxide-semiconductor field effect transistors (MOSFETs) and other devices. A MOSFET typically has a source region, a drain region, and a channel region between the source and drain. In a MOSFET device, a gate electrode is formed above and isolated from the channel by a gate dielectric to control conduction between the source and drain. [0002] The performance of such devices can be improved by reduci...

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Problems solved by technology

Similar benefits brought about by reducing the thickness of the gate dielectric, such as reduced gate blocking, are limited on small devices due to increased gate leakage current and charge penetration through the dielectric, thus Gradually destroys the transistor

Reducing the supply voltage can reduce the operating power level, but the threshold voltage of the transistor makes the above-mentioned reduction situation also limited

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