High density high reliability memory module with a fault tolerant address and command bus

Abstract

A high density high reliability memory module with a fault tolerant address and command bus. The memory module includes a rectangular printed circuit board having a first side and a second side, a length of between 149 and 153 millimeters and first and second ends having a width smaller than said length. The memory module also includes a first plurality of connector locations on the first side extending along a first edge of said board that extends the length of the board and a second plurality of connector locations on the second side extending on said first edge of said board. The memory module further includes one or more buffer devices in communication with the circuit board for accessing one or more of the four ranks of memory devices mounted on the first side and second side of the circuit board. In addition, the memory module includes a locating key having its center positioned on said first edge and located between 82 mm and 86 mm from said first end of said card and located between 66 and 70 mm from said second end of said card.

Description

technical field [0001] The present invention generally relates to a high density high reliability memory module having a fault tolerant address and command bus for use as main memory that will achieve the degree of fault tolerance and self-healing necessary for an autonomous computing system. Background technique [0002] Memory modules are well known in the art and have been and are currently being used in practical applications such as computers or other devices using solid state memory. [0003] Generally speaking, currently available main memories provide bandwidths in the range of 1.6 to 2.6 GB / s, and while some memories provide limited data path error correction, most do not provide any support for communication between the memory controller and the memory subsystem. The error correction method of the interface. Additionally, memory modules used in server products and other high-end computing systems often include redrive logic for address and command inputs, as well ...

AI Technical Summary

Problems solved by technology

[0005] Memory block density for existing solutions is typically limited to 18 or 36 devices per memory block based on factors such as memory device package size, memory block physical size, buffer, redrive or register device redrive capability, overall memory sub- factors such as system and / or module power consumption

Other possible fault-tolerance improvements, such as memory mirroring, symbol slicing, and extended forms of fault rejection and redundancy, provide enhanced memory subsystem reliability, however, due to factors such as increased cost, power, and reduced performance Negative impact, can only be considered in special applications where price is not important, since these subsystem quality enhancements are expensive to implement

Therefore, there is no solution yet for the low-end or mid-range server market