Built-in testing realization method of circuit board interconnect fault under boundary scanning environment

Abstract

The invention relates to a built-in test implementation method for circuit board interconnection faults in a boundary scan environment. The improved counting sequence algorithm and the single enable method are used as the test generation algorithms for the drive unit and the control unit respectively. The overall design of the invention is mainly composed of search Table, Test Generator and Response Analyzer are composed of three parts. This method can achieve 100% fault detection rate for all interconnection faults, including short circuit, open circuit and sluggish fault; it can avoid the problem of multi-driver conflict, so that the test can be carried out safely; and the design process is simple and easy for engineering implementation; in addition, it It also has the advantages of high reliability, fast test speed, and small hardware overhead.

Description

(1) Technical field: [0001] The invention relates to a method for realizing a built-in test (Built InTest, "BIT" for short) of circuit board interconnection faults in a boundary scan environment, and belongs to the technical field of fault detection in the process of circuit board production and maintenance. (two) background technology: [0002] Interconnect testing is a very important issue during the production and maintenance of circuit boards. For example, during the assembly process, faults such as short circuits, sluggishness, and open circuits are easily caused due to inaccurate positioning, poor solder volume control, improper temperature and time control, and other reasons. According to statistics, the number of faults on the interconnect line has accounted for more than half of the faults of the entire circuit board, and with the further improvement of the integration and complexity of the circuit board, this proportion will continue to rise. On the other hand, th...

AI Technical Summary

Problems solved by technology

However, in the above two documents, the receiving unit is classified into the driving unit (collectively referred to as the data unit), and the test stimulus is allocated to them in the same way. , cannot be loaded onto the interconnection network during the test and has no effect, thus causing additional hardware overhead for the test generator 1'

[0009] (2) The test stimuli loaded on the same interconnection network are not uniform

In Document 2 and Document 3, all the drive units are sorted uniformly and assigned to them with different test vectors. This way, different drive units belonging to the same interconnection network are assigned different test stimuli, so when these drive units are respectively When enabled, the receiving unit will observe a variety of different test responses. The diversity and disorder of the test responses will bring a lot of inconvenience to the design of the response analyzer 3', and will also increase the response analyzer 3' hardware overhead

Images