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Method for fabricating semiconductor device including recess gate

一种半导体、器件的技术，应用在制造半导体器件领域，能够解决器件特性劣化、场氧化物层12过度损伤等问题

Inactive Publication Date: 2008-05-21
SK HYNIX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, since the oxide-based hard mask pattern 13A substantially includes the same material as the field oxide layer 12, the field oxide is formed during the formation of the recess 15 and the removal of the oxide-based hard mask pattern 13A. Layer 12 is excessively damaged
Therefore, the device characteristics deteriorate

Method used

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  • Method for fabricating semiconductor device including recess gate
  • Method for fabricating semiconductor device including recess gate
  • Method for fabricating semiconductor device including recess gate

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Experimental program
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Embodiment Construction

[0020] specific implementation plan

[0021] Embodiments of the present invention relate to methods of fabricating semiconductor devices including recessed gates.

[0022] 2A-2F illustrate cross-sectional views of a method of fabricating a semiconductor device including a recessed gate according to one embodiment of the present invention.

[0023] Referring to FIG. 2A , a field oxide layer 22 is formed in a substrate 21 . Field oxide layer 22 defines the active region and the field region. An oxide-based hard mask 23 is formed on the substrate 21 . The oxide based hardmask 23 acts as a barrier layer when subsequent recesses are etched. Since the oxide-based hard mask 23 reduces damage to the substrate 21 , the oxide-based hard mask 23 is used as a hard mask. According to this embodiment of the present invention, the oxide-based hardmask 23 is not removed using a wet cleaning process (see FIG. 2E ). Therefore, the thickness of the oxide-based hardmask 23 does not have to b...

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PUM

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Abstract

A method for fabricating a semiconductor device includes forming a hard mask pattern over a substrate having a field oxide layer, etching the substrate to form a recess by using the hard mask pattern, forming a first conductive layer over the recess and the hard mask pattern, planarizing the first conductive layer, and forming a second conductive layer over the planarized first conductive layer.

Description

[0001] Cross References to Related Applications [0002] This application is based upon and claims the benefit of priority from Korean Patent Application No. 10-2006-0112645 filed in the Korean Intellectual Property Office on November 15, 2006, the entire contents of which are incorporated herein by reference. technical field [0003] The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device including a recessed gate. Background technique [0004] As semiconductor devices become highly integrated, cell transistor channel lengths decrease and ion implantation doping concentrations of substrates increase, resulting in increased junction leakage induced by increased electric fields. Therefore, it is difficult to ensure refresh characteristics of devices having a general planar transistor structure. [0005] A recessed gate process has been proposed to overcome this difficulty. ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/28
CPCH01L21/28061H01L29/66621H01L29/4236
Inventor 金锡基赵瑢泰
Owner SK HYNIX INC