Distributed type testing on-chip network router

Abstract

The invention discloses a distributing type testable chip network router, which comprises a plurality of physical transmission channels with configurable channel quantity for providing the transmission of physical data; a router configuration channel which is independent of a data transmission network and supports the connection test of the router; a plurality of channel link controllers used for finishing the response to an input request and the allocation to a virtual channel; a cross switch used for providing a full connection between an inputting virtual channel and an outputting channel; a plurality of distributing type route controllers which are distributed at the inputting virtual channel and determine the direction of microchips forwarding according to microchip head information in the channel; and a plurality of distributing type arbitration devices which are distributed in the outputting channel and determine the property ownership of the outputting channel when a plurality of inputting virtual channels request occupying the outputting channel. The router of the invention is applicable for chip network systems in the multiprocessor system chip, and has the advantages that the router is reliable, highly-efficient, testable and expandable.

Description

technical field [0001] The present invention relates to an on-chip interconnection network (On-Chip Interconnection Networks, OCINs) system used in a multiprocessor system chip (Multiprocessor Systems-on-Chip, MPSoC). A distributed testable router for networked systems. Background technique [0002] With the continuous development of integrated circuit technology and the drive of application requirements, chip design has entered the stage of a multi-processor core system chip from a single processor core system chip. In traditional design, the interconnection of functional units in a chip usually uses a shared bus. When more and more units need to be interconnected in the chip, the bus bandwidth is limited, the length increases rapidly, and the delay and power consumption on the bus also increase. These have become important factors that limit its development. In order to solve the various defects of the bus architecture, designers borrow the basic ideas in the traditional...

AI Technical Summary

Problems solved by technology

In the network-on-chip, the router and other IP (Intellectual Property) are integrated in a single chip, the distance between the routers is reduced to the millimeter level, and the metal layer inside the chip is connected to the router. Relatively limited hardware resources

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