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A hardware detector for image LSB built-in hiding information

A technology of hiding information and detectors, which is applied in the field of information security, can solve the problems that the speed of information hiding detection system is not high enough, it is difficult to meet the real-time detection of the network, and achieve the effect of improving data processing ability, shortening critical path and reducing complexity

Inactive Publication Date: 2008-09-17
ZHEJIANG UNIV
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  • Abstract
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Problems solved by technology

At present, the speed of information hiding detection system is not high enough to meet the requirements of network real-time detection

Method used

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  • A hardware detector for image LSB built-in hiding information
  • A hardware detector for image LSB built-in hiding information
  • A hardware detector for image LSB built-in hiding information

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Embodiment Construction

[0018] The purpose and effects of the present invention will become more apparent by referring to the accompanying drawings in detail of the present invention.

[0019] The detector is a hardware implementation of the RS algorithm, and has the following technical features: the image information is stored in the memory, and the address generator generates the access address according to the configuration mode, and transmits 4 pixel data to the detector in each cycle; the input pixel data First, through the replacement operation, each pixel is calculated to generate 3 replacement function values, and the corresponding replacement function value of each pixel is transmitted to the characteristic function operator through the mask vector, and the 3 characteristic function values ​​are calculated, and then through the characteristic function value The results are stored in the statistical counter, and finally, according to the results in the statistical counter, it is judged whether...

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Abstract

The invention discloses a hardware detector aiming to insert hidden information into an LSB image, which comprises an address generator, a memory, and a detection engine. Wherein, the address generator connects with the memory through an address bus of 22 bits, and the memory connects with the detection engine through a data bus of 32 bits. The detector maps the RS hidden detection algorithm to hardware to be realized, which adopts a 3-level pipeline structure, thus improves data processing efficiency; the width of the data bus of the detector is 32 bits, which possesses a strong parallel processing capability and can parallel process 4 image pixels of 8 bits at the same time; the value of image pixels is saved in the memory, and the data saved in the memory is output to the detector through a memory address generated by the address generator which supports 2 scanning modes. The invention has a very strong data processing capability and the data processing speed is much higher than the current program realized by software.

Description

technical field [0001] The invention relates to the field of image hidden information analysis and detection in the field of information security and the field of digital integrated circuit design, in particular to a hardware detector for embedding hidden information for image LSB. Background technique [0002] The widespread use of information hiding technology poses serious challenges to information security monitoring and content detection. With the development of information hiding technology, many algorithms and free tools have been developed, with which information can be hidden in images, audio, video, executable programs, text and other media. This makes the danger of improper use of information hiding technology: it can be used by spies, terrorist organizations and criminals in existing communication systems, so that secret information can be hidden in inconspicuous media, easily passing through the firewall system without If it is detected, it will pose a security...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06T1/00
Inventor 孙康史烈陈小平陈健潘雪增
Owner ZHEJIANG UNIV
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