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Display device

A display device and node technology, applied to static indicators, instruments, electrical components, etc., can solve the problems of increasing the number of output pins of the driving LSI, increasing the cost of driving the LSI, and increasing the size of the edge, so as to reduce the number of pins The effect of reducing the number of control clock lines and reducing the edge size

Active Publication Date: 2008-10-22
JAPAN DISPLAY INC +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, when the number of control clock lines is large, there is a problem that the edge size increases
In addition, the number of output pins for driving the LSI also increases, and there is a problem that the cost of driving the LSI increases.

Method used

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Experimental program
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Effect test

Embodiment 1

[0028] figure 1 A block diagram showing the configuration of the display device of this embodiment. exist figure 1 Among them, the display device of this embodiment is composed of a liquid crystal panel 211 on an insulating substrate 212 and a driving LSI (209) for driving it. In the liquid crystal panel 211, a plurality of gate lines 204 and drain lines 205 are respectively arranged in the horizontal direction and the vertical direction, and a pixel electrode 202, an opposing electrode 203, and a switching element 201 are arranged at intersections of the gate lines 204 and drain lines 205. The pixel portion forms the display area 210 . A power supply circuit 208 , a level shift circuit block 207 , and a gate driver circuit 206 are formed in a peripheral portion of the display region 210 , that is, an edge region.

[0029] The drive LSI (209) generates a control clock 215 to be supplied to the power supply circuit 208 and the level shift circuit block 207 based on the contr...

Embodiment 2

[0048] The inverter circuit of this embodiment reduces the influence of the CR time constant based on the resistive load R constituting the inverter circuit and the parasitic capacitance C of the transistor by setting a two-stage output buffer, and when the resistive load R is increased, the output is also realized. The rapid rise of the waveform. Below, use Figure 5 and Figure 6 , to illustrate this embodiment. It should be noted that the structure other than the inverter circuit is the same as that of the first embodiment, so the description thereof will be omitted.

[0049] Figure 5 is a structural diagram of the inverter circuit of this embodiment. exist Figure 5 Among them, the inverter circuit 302 includes an input inverter composed of a high-resistance load R and a transistor Tr1, an intermediate buffer composed of transistors Tr2 and Tr3, and an output buffer composed of transistors Tr4 and Tr5. The sources of the transistors Tr1 , Tr3 , and Tr5 are connected...

Embodiment 3

[0060] In this embodiment, by sharing the higher power supply voltage VDD1 used in the inverter circuit with the power supply voltage VDD of the level shift circuit block 207, the number of power supply voltages required for the operation of the built-in circuit is reduced, and the efficiency of the built-in circuit is reduced. Controls the reduction in the number of clock lines.

[0061] Figure 7 is a configuration diagram of the level shift circuit block 207 of this embodiment. exist Figure 7 , the level shift circuit block 207 is used to increase the figure 1 The level shift circuit 301 for controlling the amplitude of the control clock output by the drive LSI (209) and the inverter circuit 302 for generating the inverted clock INB required to operate the level shift circuit 301 are constituted. This inverter circuit 302 is the same as the inverter circuit 302 used in Embodiments 1 and 2, and its circuit configuration and operation were described in Embodiments 1 and 2...

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Abstract

The invention provides a display device which forms an inverter circuit 302 by adopting an input phase inverter Tr1 of high resistance load R and an output buffer formed by two transistors Tr2 and Tr3 connected in series. When the power voltage of the input phase inverter is VDD1, the power voltage of output buffer is VDD2 and the threshold voltage of the transistor is Vth, the power voltage is supplied to satisfy inequality VDD1 >VDD2+Vth. The high resistance load R enables elevation and declination fast and reduces the consumed current.

Description

technical field [0001] The present invention relates to a drive circuit-integrated liquid crystal display device including an inverter circuit. Background technique [0002] TFT (Thin Film Transistor) type liquid crystal display devices in which switching elements are provided in pixel portions are widely used as display devices for personal computers and the like, and demand for display devices for small mobile terminals such as mobile phones is also increasing. In TFT liquid crystal displays, while high image quality and low power are required, low cost requirements are also very strong. Especially in small displays for mobile phones, the cost of driving LSI for driving panels accounts for a large proportion, so it is required to drive LSI reduces costs. [0003] As a low-cost method for driving LSIs, conventionally, a high withstand voltage circuit such as a power supply circuit or a driving circuit mounted on a driving LSI is formed on a glass substrate by the same proc...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G09G3/36H03K19/017
CPCG09G3/3696G09G2300/0408G09G2310/0289
Inventor 梶原久芳万场则夫宫泽敏夫槙正博
Owner JAPAN DISPLAY INC
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