[0030] image 3 This is the shift register of the first embodiment of the present invention. The shift register includes an input unit 311, a feedback unit 312, a reset unit 313, and an output unit 314. In this embodiment, each unit is composed of at least one switch. For example, the input unit 311 includes a switch 301, the feedback unit 312 includes a switch 302, the reset unit 313 includes switches 303 and 305, and the output unit 314 includes a switch 304. The switches 301 to 305 all have a first terminal, a second terminal, and a control terminal, and these switches all determine whether to turn on or not according to the signal received by the control terminal.
[0031] The first terminal of the switch 301 of the input unit 311 receives an input signal IN, and the control terminal thereof receives a clock signal CLK1 (ie, the first signal) to determine whether to conduct the input signal IN to the second terminal. The first terminal of the switch 304 of the output unit 314 receives the clock signal CLK2 (ie the second signal), the second terminal outputs an output signal OUT, and the control terminal is coupled to the second terminal of the switch 301 to determine whether to The clock signal CLK2 at one end is output to the second end as the output signal OUT. The switch 304 can maintain the voltage of its control terminal at least until the clock signal CLK2 turns to a high level. The first terminal of the switch 302 of the feedback unit 312 is coupled to the second terminal of the switch 301, and its control terminal receives a clock signal CLK2 to determine whether to feed back the output signal OUT connected to the second terminal back to the first terminal connected The output unit. The first terminal of the switch 303 of the reset unit 313 is coupled to the second terminal of the switch 302, and the second terminal of the switch 303 is coupled to a low level signal V of the system. L , In this embodiment, the low potential signal V L If it is not higher than the low level of CLK2, the control terminal receives the clock signal CLK1 to determine whether to reset the output signal of the output unit. The first end of the switch 305 is coupled to the second end of the switch 304 and the first end of the switch 303, and the second end of the switch 305 is also coupled to the low-level signal V L, Its control terminal receives the reset signal RES. In addition, when the shift register is applied to a driving device of a liquid crystal display, the reset signal RES can be an OE (Output Enable) signal, and the switch 305 determines whether or not according to the reset signal RES Reset the output signal of the output unit. In addition, when the shift register is applied to a driving device of a liquid crystal display, the low potential signal V L It can be a VL signal.
[0032] In this embodiment, the switches 301 to 305 can be implemented by NMOS transistors, PMOS transistors, thin film transistors, BJT transistors, or other electronic switching elements. In addition, the internal implementation of the input unit 311, feedback unit 312, reset unit 313, and output unit 314 in this embodiment is not image 3 The illustration is a limitation, and each unit can also be composed of multiple switches or implemented in any other circuit form that can produce the above-mentioned functions.
[0033] Figure 4 As basis image 3 A signal timing control diagram of the circuit shown, Figure 4 Each signal name in corresponds to image 3 The name of each signal in, where the input signal IN is a pulse signal, the pulse signal is the same as the pulse enable period of the clock signal CLK1, and the pulse enable period of the clock signal CLK1 and the clock signal CLK2 are different, and The pulse period of the reset signal RES is located between the pulse periods of the clock signal CLK1 and the clock signal CLK2. In other words, the duty cycle of the clock signal CLK1 and the clock signal CLK2 must be less than 50% of the system clock cycle. In this embodiment, the preferred duty cycle of CLK1 and CLK2 is less than 48.5%, so that the pulse of the reset signal RES The wave period can be located between the pulse periods of the clock signal CLK1 and the clock signal CLK2. In addition, when CLK1 and CLK2 have the same pulse width, the preferred clock width ratio of the RES signal to CLK1 and CLK2 is less than 0.03. The optimal operation timing disclosed in this embodiment is that the pulse width of RES is 1.6 microseconds. (us), and the width of the clock signals of CLK1 and CLK2 is 63.5 microseconds (us).
[0034] Refer to image 3 and Figure 4. When the input signal IN and the clock signal CLK1 are at a high level, and the clock signal CLK2 is at a low level, the switch 301 and the switch 303 are turned on, so the shift register can use the clock signal CLK1 to open the switch 301 to sample the input signal IN , And use the switch 303 to first couple the output terminal of the shift register to the low potential terminal V of the system L , To reset the output terminal, this low potential terminal V L Not higher than the low level of CLK2. Then, the clock signal CLK1 turns to a low potential, and the reset signal RES turns to a high potential. At this time, the switch 305 is turned on to couple the output terminal OUT of the output unit to the low potential terminal V of the system. L , To further reset the output terminal OUT, at this time the clock signal CLK2 continues to maintain a low level, the switch 304 uses its own parasitic capacitance to store the charge supplied by the sampled input signal IN to maintain its gate voltage at least It is maintained until the clock signal CLK2 turns to a high level. Since this sustain time is determined by the size of the transistor used as the switch 304, the size of the transistor used as the switch 304 must be large enough to maintain its on-time until the clock signal CLK2 turns to a high level.
[0035] Then, the clock signal CLK2 turns to a high level, and the clock signal CLK1 and the reset signal RES both assume a low level. Since the switch 304 is still in the on state, the output signal OUT can be output. At the same time, the switch 302 of the feedback unit is also turned on, so the output signal OUT can be fed back to the control terminal of the switch 304 of the output unit to ensure that the switch 304 of the output unit can completely output the output signal OUT.
[0036] The shift register of the present invention can reduce or avoid the use of passive components, so the size of the circuit can be reduced. Moreover, users can make use of the space surplus to build an extra set of shift registers with the same architecture. When one of the two sets of shift registers fails to operate normally, they can use the other set of shift registers. To replace.
[0037] According to the teaching of the above-mentioned embodiment, the user can use multiple shift registers as in the first embodiment to construct a shift register device, such as Figure 5 Shown as one with N such as image 3 The shift register shown is a stack of shift registers. in Figure 5 Among them, IN represents the input signal, OUT(1)~OUT(N) are respectively represented as the output signal of the shift register 501~N, and CLKS1 and CLKS2 represent two different clock signals, and they are connected in a staggered manner. CK1P and CK2P connected to each shift register, CK1P is expressed as image 3 The circuit receives the control end of the clock signal CLK1, and CK2P is expressed as image 3 The circuit receives the control end of the clock signal CLK2. The IP in each shift register is expressed as image 3 The input terminal of the input unit receiving the input signal IN, RP is expressed as image 3 The reset unit receives the reset terminal of the reset signal RES. Therefore, when the input signal IN to the (N-1)th shift register is high, coupled with the different timing signals of CLKS1 and CLKS2, after a clock signal time is delayed, it will be output at OUT(N-1) A high-level signal, and the OUT(N-1)th signal also becomes the input signal of the Nth shift register, and then the OUT(N-1)th signal is reset back to a low-level signal by the RES signal. Similarly, when the input signal IN to the (N)th shift register is high, after a clock signal time is delayed, a high voltage signal will be output at OUT(N), and then OUT(N) will be Will be reset back to a low level signal by the RES signal.
[0038] Figure 6 for Figure 5 The signal timing diagram of the circuit shown, Figure 6 Each signal name in corresponds to Figure 5 The name of each signal in. As mentioned in the foregoing article, the duty cycle of the clock signal CLKS1 and the clock signal CLKS2 must be less than 50% of the system clock cycle, so that the pulse period of the reset signal RES can be located in the pulse of both the clock signal CLKS1 and the clock signal CLKS2 Between waves, and by Figure 5 It can be seen that each stage of shift register uses the same RES reset signal. In this way, an N-stage shift register device only needs N shift registers, and the N+1th stage shift register is no longer needed to provide the Nth stage reset signal. Therefore, the shift register device of the present invention only needs N shift registers to operate.
[0039] By image 3 The teachings of the relevant instructions, after appropriate modification image 3 The circuit shown can also be changed into other types of shift registers, which can also perform signal shift operations without using the reset signal RES, such as Figure 7 Shown. Figure 7 It is a shift register according to the second embodiment of the present invention. Control image 3 and Figure 7 The circuit shown can be clearly found, Figure 7 The circuit is only changing image 3 The signal received by the control end of the switch 305 is changed from the original reset signal RES to the clock signal CLK1 to form a reset unit 714.
[0040] In addition, such as Figure 8 Shown is the shift register of the third embodiment of the present invention. Control Figure 7 and Figure 8 The circuit shown can be clearly found, Figure 8 The circuit is Figure 7 The reset unit 714 in the circuit is simplified, the setting of the switch 705 is omitted, and the reset unit 814 is formed. due to Figure 7 and Figure 8 The circuits shown only use the clock signal CLK1 to reset their output terminals. Therefore, both circuits only need to use the clock signals CLK1 and CLK2 to perform signal shift. In addition, compare the first, second and third implementations of the present invention. For example, it is also explained that the reset signal RES can be a different signal. Similarly, according to the flexible application of the reset signal RES in the foregoing embodiments, in other embodiments, the control terminals of the switch 305 and the switch 705 in the reset unit of the first and second embodiments of the present invention may also be The other reset signal is coupled without being limited to the clock signal CLK1, and the pulse enable period of the other reset signal can be designed to be the same as the clock signal CLK1. Picture 9 for Figure 7 and Figure 8 The signal timing diagram of the circuit shown, Picture 9 Each signal name in corresponds to Figure 7 and Figure 8 The name of each signal in.
[0041] By the above Figure 7 and Figure 8 The teaching of the circuit, the user can use multiple Figure 7 or Figure 8 The shift register shown to construct a shift register device, such as Picture 10 Shown. Picture 10 The shift register device in includes shift registers 1001~K, and these shift registers all use Figure 7 or Figure 8 The shift register architecture shown. In the figure, IN is represented as the input signal, OUT(1)~OUT(K) are respectively represented as the output signal of the shift register 1001~K, and CLKS1 and CLKS2 respectively represent two different clock signals. As for the IP in each shift register expressed as Figure 7 or Figure 8 The circuit shown receives the input terminal of the input signal IN, CK1P is expressed as Figure 7 or Figure 8 The circuit shown receives the control end of the clock signal CLK1, and CK2P is expressed as Figure 7 or Figure 8 The circuit shown receives the control end of the clock signal CLK2, and CLKS1 and CLKS2 are connected to the CK1P and CK2P of each shift register in a staggered connection.
[0042] Such as Picture 10 As shown, when the input signal IN to the (K-1)th shift register is high, with CLKS1 and CLKS2 different timing signals, after a clock signal time is delayed, it will be in the OUT(K-1)th shift register. ) Outputs a high level signal, and at the same time, the OUT(K-1)th signal becomes the input signal of the Nth shift register, and then the OUT(K-1)th signal will be reset back to a low level signal by the CLKS1 signal. Similarly, when the input signal IN to the (K)th shift register is high, after a clock signal time is delayed, a high voltage signal will be output at OUT(K), and then OUT(K) will be Will be reset back to a low level signal by the CLKS2 signal.
[0043] In the above embodiments, the main features of the shift register of the present invention are described as having an input unit, an output unit, a reset unit and a feedback unit, and it is also explained that there are multiple sets of shift registers with this feature. A shift register device composed of registers. This shift register device has features such as staggered CLKS1 and CLKS2 connections and a RES reset signal. In other embodiments, CLKS1 can even be used as the source of the reset signal RES and can Achieve the function of displacement of the input signal. In addition, because the present invention can reduce or avoid the use of passive components, the circuit size and the area occupied by the circuit can be reduced, and the yield rate can be improved due to the simplification of the components.
[0044]The technical content and technical features of the present invention have been disclosed above, but those of ordinary skill in the art may still make various substitutions and modifications based on the teaching and disclosure of the present invention without departing from the spirit of the present invention. Therefore, the protection scope of the present invention should not be limited to the disclosed embodiments, but should include various replacements and modifications that do not deviate from the present invention, and are covered by the appended claims.
