Shallow groove isolation structure and floating grid manufacture method

Abstract

Disclosed is manufacturing method of a shallow groove structure, which includes firstly providing a substrate with a formed patterned mask layer which is provided with an opening, then forming a gap wall on the lateral wall of the patterned mask layer, the gap wall has an obtuse angle between the lateral wall on the opening side and the upper surface of the patterned mask layer, and then, using the patterned mask layer and the gap wall as masks, and forming a groove in the substrate, afterward, filling a dielectric layer in the groove, and finally removing the patterned mask layer and the gap wall.

Description

technical field [0001] The invention relates to a semiconductor process, and in particular to a shallow trench isolation structure and a manufacturing method of a floating gate. Background technique [0002] With the advancement of semiconductor technology, the size of components is also continuously reduced. When the size of the components enters the deep sub-micron range, or even finer dimensions, the probability of short circuits between adjacent components will increase, so how to effectively isolate the components becomes very important . Generally speaking, an isolation structure is usually added between elements in the process to avoid short circuits, and the more commonly used method today is the shallow trench isolation (STI) process. Since the shallow trench isolation structure is often an important key that affects reliability, such as the occurrence probability of leakage current, the shallow trench isolation structure process plays an important role in the adv...

AI Technical Summary

Problems solved by technology

When the silicon oxide layer 130 is formed by the known high-density plasma chemical vapor deposition method, due to its poor ditch filling ability, the silicon oxide layer 130 cannot be completely filled in the trench 120, and the hole 140 is formed.

The hole 140 will cover the process gas, and these gases will diffuse inside the wafer, which will reduce the performance of the semiconductor element, and even cause a short circuit, which will affect the subsequent process.

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