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Metal interlayer medium contact hole preparation method

A manufacturing method and metal layer technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as over-etching, gate etching, and damage to gate conductivity, so as to reduce the etching depth and improve the finished product. rate, improve the effect of gate over-etching phenomenon

Inactive Publication Date: 2008-11-26
SEMICON MFG INT (SHANGHAI) CORP
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  • Abstract
  • Description
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  • Application Information

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Problems solved by technology

The height of the interlayer dielectric corresponding to the contact window of the active region is higher than the interlayer dielectric corresponding to the gate contact window, so that in the process of etching the contact hole, the gate is often over-etched and the conductivity of the gate is damaged.
[0003] In the prior art, there is a stop layer (stop layer) between the active region and the gate of the semiconductor device and the inter-metal dielectric, and the stop layer reduces to a certain extent during the process of etching the contact hole of the inter-metal dielectric. Overetching of the gate, but overetching often occurs

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  • Metal interlayer medium contact hole preparation method
  • Metal interlayer medium contact hole preparation method
  • Metal interlayer medium contact hole preparation method

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Embodiment Construction

[0014] A preferred embodiment of the method for manufacturing the contact hole of the inter-metal dielectric of the present invention will be described in detail below with reference to the accompanying drawings.

[0015] The manufacturing method of the contact hole of the metal interlayer dielectric of the present invention comprises the following steps:

[0016] Please refer to FIG. 1 , providing a substrate of a semiconductor device, which includes a gate 2 as an emitter and an active area (active area) 1 formed on a semiconductor substrate on both sides of the gate;

[0017] Deposit and form metal interlayer dielectric (ILD) 3 on gate 2 and active region 1, which is used to isolate metal interconnection lines and also to support upper layer metal lines, generally using borophosphosilicate glass (that is, doped with boron and Phosphorous low-temperature silicon dioxide), as an inter-metal dielectric 3;

[0018] The step of depositing barrier layer 4 is different from the p...

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Abstract

The invention discloses a manufacturing method of contact holes for medium between metal layers, which relates to the semiconductor manufacturing area. The manufacturing method includes steps of providing a semiconductor element substrate which comprises a grid and active areas positioned on bilateral sides of the grid, forming medium between metal layers on the grid and the active area by deposition, forming a barrier layer on the medium between metal layers by deposition, carrying out the first lighting step, and carrying out the first etching step, etching other parts of the barrier layer except for a part of the barrier layer corresponding to the grid, carrying out the second lighting step, carrying out the second etching step, and forming contact holes which are respectively communicated with the grid and the active areas on the medium between metal layers. Compared with the prior art, the manufacturing method avoids or at least reduces over-etching to the grid by arranging a barrier layer on the medium between metal layers, and increases yield of products.

Description

technical field [0001] The invention relates to the manufacturing technology in the field of semiconductors, in particular to a method for manufacturing a contact hole of an intermetallic dielectric. Background technique [0002] The active area and the gate of the semiconductor device are electrically connected to other metal interconnection layers by filling metal in the contact hole of the inter-metal dielectric. The height of the interlayer dielectric corresponding to the contact window of the active region is higher than that of the interlayer dielectric corresponding to the gate contact window. In this way, during the process of etching the contact hole, the gate is often over-etched and the conductivity of the gate is damaged. [0003] In the prior art, there is a stop layer (stop layer) between the active region and the gate of the semiconductor device and the inter-metal dielectric, and the stop layer reduces to a certain extent during the process of etching the con...

Claims

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Application Information

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IPC IPC(8): H01L21/768H01L21/31
Inventor 宋伟基石磊
Owner SEMICON MFG INT (SHANGHAI) CORP