High-capacity FLASH solid memory controller

Abstract

The present invention relates to a high-capacity FLASH solid-memory controller, and comprises a data cache unit, a checking code cache unit, a checking code generating and correcting unit, a bad block auto-processing unit and a dual cache control unit. The checking code generating and correcting unit is used for receiving the data transmitted from an external microcontroller through the microcontroller interface, generating the checking code according to the received data, and transmitting the data and the checking code to the dual cache control unit. The data transmitted from the dual cache control unit are corrected and are transmitted to the external microcontroller through the microcontroller interface. The bad block auto-processing unit is used for automatically identifying the bad memory block in an external FLASH memory, and distributing the replacement block, so as to guarantee the regular reading and writing of the external FLASH memory. The high-capacity FLASH solid-memory controller can be operated without the user. The dual cache control unit is communicated with the microcontroller interface, the FLASH interface or the bad block auto-processing unit, so as to realize the data writing or reading of the data cache unit and the checking code cache unit.

Description

technical field [0001] The invention belongs to the field of FLASH memory, and relates to a controller of a large-capacity FLASH solid-state memory. Background technique [0002] Flash memory FLASH is currently the most cost-effective and reliable rewritable, non-volatile memory. Large-capacity FLASH solid storage is a very complex type of storage device, and its complexity is reflected in the complex structure of the memory bank and the complex function sequence. Commonly used large-capacity FLASH solid storage, its storage body is often composed of different levels of storage structures such as data bytes, information bytes, half pages, pages, and blocks; its functions generally include full-chip erase, block erase, and page programming. , read status, read ID, read data, read information, etc.; its timing basically consists of steps such as command operation, address operation, data operation, waiting operation, and query operation. [0003] What's more special is that ...

AI Technical Summary

Problems solved by technology

[0004] Existing FLASH solid storage controllers are mainly composed of host interface (including command register, address cache, etc.), CPU, data memory (including ROM and RAM) and FLASH interface. These FLASH solid storage controllers often only focus on compatibility with multiple The host communication protocol supports a variety of FLASH interfaces, but ignores the errors generated in data transmission and the defects of FLASH itself. For example, a FLASH firmware disclosed in the U.S. patent No. This kind of solid storage controller has poor data error correction ability, and cannot deal with the defects of FLASH solid storage itself, and is prone to data errors, which cannot meet the high reliability requirements of the aerospace military industry

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