Signal receiver

Abstract

The invention relates to a receiving circuit, which comprises a transmission gate, a pulling-down unit, a boost capacitor, a bleeder circuit and a receiving unit. The transmission gate determines whether a transmission signal is conducted according to a control signal. The pulling-down unit determines whether a voltage at one endpoint of the boost capacitor is pulled down. The boost capacitor boost can input voltage of the receiving unit. The bleeder circuit is controlled by the control signal and transmits a bleeder voltage to the other endpoint of the boost capacitor. When a signal is input, the boost capacitor boosts the input signal, and the problem of not enough current caused by the over critical voltage of a transistor is solved, so as to enable the receiving unit to achieve the total amplitude.

Description

technical field [0001] The present invention relates to a receiving circuit, and in particular to an improved receiving circuit which cannot achieve full amplitude. Background technique [0002] For the receiving circuit of DRAM (Dynamic Random Access Memory, DRAM), if the N-type metal oxide semiconductor of the N-type differential amplifier (N-differential amplifier) ​​has a high threshold voltage, it is easy to cause the entire circuit to fail. current limit, and the duty cycle of the receiver cannot be balanced (ie, 50%). [0003] Such as figure 1 Shown is a conventional receiver. This receiver includes transistors M1 ~ M4, an inverter INVR and a resistor R D . The gate terminal of the transistor M1 is connected to the node N1 , the source terminal is connected to the voltage source VDD, and the drain terminal is connected to the input terminal of the inverter INVR and the drain terminal of the transistor M3 . The gate terminal of the transistor M2 is connected to th...

AI Technical Summary

Problems solved by technology

Thus causing the drain-source current I of transistor M3 DS Insufficient enough to support the amplitude of the input terminal of the inverter INVR, resulting in the phenomenon that the duty cycle of the output voltage Vout cannot be balanced (that is, the duty cycle of the output voltage Vout cannot be close to 50%)

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