Discrete-time programmable-gain analog-to-digital converter (adc) input circuit and method

Abstract

The present invention discloses a discrete time programmable gain analogue-digital conversion (ADC) input circuit which has input signal and common-mode current zero setting. The invention provides a high input impedance grade which is absolutely independent from the magnitude of input capacitor and gain setting of input signal. When an input voltage is sampled with one or a plurality of reference capacitors, the reference capacitor is loaded with a net charge of reference voltage controlled by a quantizer at a before clock phase. As the charge exerted from input voltage source is dependent on quantization error and input noise voltage to a large extent, the circuit has high signal input impedance. The reference capacitor can charge at a third clock phase, thus the input signal is released from the capacitor dependently from the voltage. An additionally sampling capacitor can be discharged in the first clock phase, and furthermore is coupled to the reference capacitor in parallel at the second clock phase period thereby setting the gain relatively to the input voltage.

Description

technical field [0001] The present invention relates generally to discrete-time input circuits, and more particularly to a discrete-time analog-to-digital converter (ADC) input circuit having input signals and common-mode current nulling. Background technique [0002] Measurement input circuits for analog-to-digital converters must usually be able to handle large common-mode voltage differences between the input signal and the feedback reference voltage, especially in circuits such as AC line power or DC measurement circuits, and in test equipment such as digital voltmeters (DVM ) and other applications. Even with transformers or resistive dividers, the dynamic range required for common applications generally requires one or more programmable gain stages to preserve the signal-to-noise ratio (SNR) at the input and a high input impedance buffer stage to avoid adding to the The source under test adds load, especially if the source under test may have a large input voltage ran...

AI Technical Summary

Problems solved by technology

In some embodiments, a common-mode voltage reference is provided to offset the common-mode voltage of the measurement source, thereby simplifying the snubber circuit requirements, but such embodiments usually require an external IC terminal, and the common-mode voltage source buffering

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