Full digital phase locking loop

Abstract

The present invention provides an all-digital phase-locked loop comprising a reference signal frequency indicator for receiving reference signals with a reference frequency and output a frequency indicating value; a phase frequency detector for comparing reference signals and frequency dividing signals and output phase difference pulses; a time to digit conversion circuit for receiving phase difference pulses and multiple output signals and generating phase difference values; a digital controller for receiving phase difference values and frequency indicating values and generating control values; a delta-sigma modulator for modulating control values; a digitally controlled oscillator for receiving modulated control values and outputting oscillation signals with a digital control frequency; a frequency divider for generating frequency dividing signals by making the digit control frequency divided by a divisor; a multi-phase generator for receiving output oscillation signals and generating output signals with a fixed phase difference. The phase-locked loop which does not change with the changes of technics, supply voltage and the like can maintain the loop dynamic and damping factor at a fixed value.

Description

technical field [0001] The present invention relates to a phase locked loop circuit (PLL for short), in particular to an all digital phase locked loop (all digital PLL) with self-correcting loop stability and bandwidth, and has nothing to do with process, Phase-locked system for supplied voltage and temperature. Background technique [0002] Please refer to FIG. 1 , which shows a known analog PLL. The phase locked loop 100 includes a phase frequency detector (phase frequency detector) 10, a charge pump (charge pump) 20, a loop filter (loop filter) 30, a voltage controlled oscillator (voltage controlled oscillator) 40 and a frequency divider (frequency divider) 50. Wherein, the reference signal Sref11 having a reference frequency Fref is generated by, for example, a reference oscillator (reference oscillator, not shown), and the reference signal Sref11 and a frequency divided signal (frequency divided signal, Sfd) 52 simultaneously input the phase frequency detector 10. T...

AI Technical Summary

Problems solved by technology

The above example is only when the frequency of the reference signal is fixed. When the frequency of the reference signal also changes, more pruning registers are needed to store the KP value and KI value.

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