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Mounted structure

A technology of structures and semiconductors, which is applied in the direction of electric solid-state devices, semiconductor devices, printed circuits assembled with electrical components, etc., and can solve problems such as deterioration of joint quality

Inactive Publication Date: 2009-05-06
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, if the mounting temperature rises, the substrate 1 warps and the bonding quality between the substrate 1 and the semiconductor packages 2a and 2b deteriorates, and the bonding quality between the substrate 1 and the chip component 3 deteriorates.

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment approach 1

[0037] Figure 1A , Figure 1B Embodiment 1 of this invention is shown.

[0038] Figure 1A is the floor plan, Figure 1B Yes Figure 1A The A-AA sectional view, Figure 1B A part of it is shown enlarged.

[0039] Semiconductor packages 2a, 2b as semiconductor elements and chip components 3 as electronic components other than the semiconductor elements are mounted on the substrate 1 . The chip component 3 is mounted between two adjacently arranged semiconductor packages 2a, 2b such that it enters a space between the semiconductor packages 2a, 2b. A sealing resin 4 is provided to seal the two semiconductor packages 2 a , 2 b and the five chip components 3 . The semiconductor packages 2 a , 2 b and the chip component 3 are mounted on the substrate 1 with solder 5 . Here, the chip component 3 is mounted in the middle of the semiconductor packages 2a, 2b.

[0040] Depend on Figure 1B It can be seen that between the plurality of semiconductor packages 2a, 2b and the subs...

Embodiment approach 2

[0071] In the second aspect of the present invention, for Figure 1A , Figure 1B In the embodiment of the present invention, the thickness of the substrate 1 was changed, and a thermal cycle life test was performed. The thermal cycle life test is the same as that of the first embodiment. The results are shown in Table 2 below. This Table 2 shows the thermal cycle characteristics when the thickness of the substrate 1 was changed in the range of 0.25 to 0.80 mm.

[0072]

[0073] When the substrate 1 is thick, the substrate 1 itself is held well even if the temperature changes, so there is little warping, etc. However, in a thin mounting structure with a thickness of the substrate 1 of 0.5 mm or less, the substrate 1 warps due to temperature changes. In other words, when only using low-temperature solder with a melting point below 200° C., the joint quality is poor. Therefore, if the sealing resin 4 is not used for overall sealing, joint defects will occur and the life wi...

Embodiment approach 3

[0075] Embodiment 3 is for Figure 1A , Figure 1B Example of the distance between the semiconductor packages 2a, 2b in .

[0076] Figure 1A , Figure 1B Among them, the bonding material is composed of Sn-Bi solder used in Embodiment 2, and chip components 3 are mounted between a plurality of BGA / LGA semiconductor packages 2a and 2b in the component mounting area on the substrate 1 . In this case, the chip component 3 is mounted on the substrate 1 between the semiconductor packages 2a and 2b adjacent to the coating point P, and when the sealing resin 4 is applied to the semiconductor packages 2a, 2b and the chip component 3, the semiconductor package is changed. The results of the distance between 2a and 2b are shown in Table 3 below.

[0077]

[0078] As can be seen from Table 3, if the distance between adjacent semiconductor packages 2 a and 2 b is 40 mm or less, the sealing resin 4 can be stably applied. However, if the semiconductor packages 2a and 2b are arranged a...

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Abstract

A plurality of semiconductor elements is adjacently mounted on a substrate by a solder with a melting point of 200 DEG C. or lower, an electronic part other than the semiconductor elements is mounted on the substrate between the adjacently mounted semiconductor elements by a solder with a melting point of 200 DEG C. or lower, and spaces between the plurality of semiconductor elements and the substrate, spaces between the electronic part and the substrate, and spaces between the plurality of semiconductor elements and the electronic part are integrally molded with a molding resin.

Description

technical field [0001] The present invention relates to a mounting structure in which a semiconductor element and electronic components other than the semiconductor element are mounted on a substrate. Background technique [0002] In the past, the bonding materials used to install semiconductor elements and electronic components other than the semiconductor elements generally adopt leaded Sn-Pb solder materials, especially with 63Sn-37Pb eutectic composition (63% by weight Sn and 37% by weight Composition of Pb) Sn-Pb eutectic solder material. [0003] Figure 4A , Figure 4B Middle indicates a mounting structure in which solder material is used as the bonding material. [0004] Figure 4A is the floor plan, Figure 4B Yes Figure 4A The A-AA sectional view, Figure 4B A part of it is shown enlarged. Semiconductor packages 2 such as BGA (Ball Grid Array) / LGA (Land Grid Array) and chip components 3 other than the semiconductor package are mounted on the substrate 1 by so...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L25/00H01L23/488H01L23/31H05K1/18H05K3/34
CPCB23K35/264H01L2924/19105H01L2924/19043H01L2224/73204H01L2924/01079H01L24/32H01L24/13H01L2924/01322H05K3/3463H01L24/29H05K3/3484H01L2924/19041H01L24/16H01L2224/16225H01L2924/01087H05K3/284H05K3/321H01L2224/32225H05K3/3485H01L2924/3512H01L2924/00H01L23/02B23K1/00H05K3/34
Inventor 山口敦史宫川秀规酒谷茂昭松野行壮
Owner PANASONIC CORP
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