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Giant piezoresistance produced by interface traps at the nanoscale and its fabrication method

An interface trap, nano-scale technology, applied in the field of giant piezoresistance, can solve problems such as the inability to improve the piezoresistive effect of silicon materials

Active Publication Date: 2011-12-14
SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

From this point of view, the nano-effect cannot greatly improve the piezoresistive effect of silicon materials.

Method used

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  • Giant piezoresistance produced by interface traps at the nanoscale and its fabrication method
  • Giant piezoresistance produced by interface traps at the nanoscale and its fabrication method
  • Giant piezoresistance produced by interface traps at the nanoscale and its fabrication method

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Experimental program
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Effect test

Embodiment 1

[0050] 1. Use (100) SOI silicon wafers, the thickness of the surface silicon is 275nm, and the thickness of the buried silicon oxide is 1.25μm, such as image 3 shown;

[0051] 2. Dry thermal oxidation generates a 180nm oxide layer, photolithography retains the oxide layer in the lead area, and removes the oxide layer in other areas;

[0052] 3. Dry thermal oxidation generates an oxide layer of 85nm, photolithography retains the oxide layer in the lead area, and removes the oxide layer in other areas;

[0053] 4. Dry thermal oxidation generates a 170nm oxide layer and removes all oxide layers;

[0054] 5. Dry thermal oxidation to generate a 60nm oxide layer, photolithographic resistance pattern, buffered silicon dioxide etching solution to etch the oxide layer, and tetramethylammonium hydroxide solution to etch silicon to the buried layer of silicon dioxide to form a resistance pattern;

[0055] 6. Dry thermal oxidation generates a 50nm oxide layer to protect the side of the...

Embodiment 2

[0066] 1. Use (100) SOI silicon wafers, the thickness of the surface silicon is 275nm, and the thickness of the buried silicon oxide is 1.25μm, such as image 3 shown;

[0067] 2. Dry thermal oxidation generates a 180nm oxide layer, photolithography retains the oxide layer in the lead area, and removes the oxide layer in other areas;

[0068] 3. Dry thermal oxidation generates an oxide layer of 85nm, photolithography retains the oxide layer in the lead area, and removes the oxide layer in other areas;

[0069] 4. Dry thermal oxidation generates a 170nm oxide layer and removes all oxide layers;

[0070] 5. Dry thermal oxidation to generate a 100nm oxide layer, photolithography resistance pattern, BOE etching oxide layer, TMAH etching to buried silicon dioxide, forming resistance pattern;

[0071] 6. Dry thermal oxidation generates an oxide layer of 80nm, which protects the side of the resistor from the external environment, such as Figure 4 shown;

[0072] 7. Boron ion imp...

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Abstract

The invention relates to the giant piezoresistive effect produced by the action of interface traps at the nanometer scale and a manufacturing method of the nanometer giant piezoresistor, which belongs to the field of micro-electromechanical systems. The specific feature of the giant piezoresistor in the present invention is that the thickness of the piezoresistor is on the order of nanometers, and the piezoresistive effect comes from the electron trap effect at the interface between silicon and silicon dioxide. The piezoresistive effect of traditional bulk silicon comes from the change of carrier mobility under stress, while the giant piezoresistivity at the nanoscale described in the present invention is that the electronic trap at the interface between silicon and silicon dioxide changes the current carrying capacity under stress. produced by the concentration of the sub. As the piezoresistive thickness decreases, the interface effect accounts for a larger proportion, and the piezoresistive effect produced by the interface trap becomes more obvious. The piezoresistor produced by the invention has the advantages of large piezoresistive coefficient, the same change in the resistance value of the transverse piezoresistor and the longitudinal piezoresistor, and is compatible with semiconductor technology, and can be used in sensors and micro-electromechanical systems.

Description

technical field [0001] The invention relates to a giant piezoresistor produced by the action of interface traps at the nanometer scale and a manufacturing method of the nanometer giant piezoresistor, belonging to the field of micro-electromechanical systems. Background technique [0002] In 1954, American scientist Smith discovered the piezoresistive effect of semiconductor materials (C.S.Smith, "Piezoresistance Effect in Germanium and Silicon," Physical Review, vol.94, p.42, 1954.). Subsequently, scientists conducted in-depth research on the piezoresistive effect of silicon materials. Because silicon piezoresistive has the advantages of high piezoresistive coefficient and compatibility with semiconductor manufacturing, the piezoresistive effect of silicon material has been widely used as a detection method in sensors of MEMS, such as pressure sensors, acceleration sensors and various A biochemical sensor with a cantilever beam structure. [0003] Although the piezoresisti...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): B82B1/00B82B3/00G01L1/18G01P15/12H01L21/18
Inventor 杨永亮李昕欣
Owner SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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