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Giant piezoresistance effect generated by nanometer scale interface trap and method for manufacturing the same

An interface trap and nanoscale technology, applied in the field of giant piezoresistive, can solve the problem of not being able to improve the piezoresistive effect of silicon materials

Active Publication Date: 2009-07-08
SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

From this point of view, the nano-effect cannot greatly improve the piezoresistive effect of silicon materials.

Method used

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  • Giant piezoresistance effect generated by nanometer scale interface trap and method for manufacturing the same
  • Giant piezoresistance effect generated by nanometer scale interface trap and method for manufacturing the same
  • Giant piezoresistance effect generated by nanometer scale interface trap and method for manufacturing the same

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0050] 1. Use (100) SOI silicon wafers, the thickness of the surface silicon is 275nm, and the thickness of the buried silicon oxide is 1.25μm, such as image 3 shown;

[0051] 2. Dry thermal oxidation generates a 180nm oxide layer, photolithography retains the oxide layer in the lead area, and removes the oxide layer in other areas;

[0052] 3. Dry thermal oxidation generates an oxide layer of 85nm, photolithography retains the oxide layer in the lead area, and removes the oxide layer in other areas;

[0053] 4. Dry thermal oxidation generates a 170nm oxide layer and removes all oxide layers;

[0054] 5. Dry thermal oxidation to generate a 60nm oxide layer, photolithographic resistance pattern, buffered silicon dioxide etching solution to etch the oxide layer, and tetramethylammonium hydroxide solution to etch silicon to the buried layer of silicon dioxide to form a resistance pattern;

[0055] 6. Dry thermal oxidation generates a 50nm oxide layer to protect the side of the ...

Embodiment 2

[0066] 1. Use (100) SOI silicon wafers, the thickness of the surface silicon is 275nm, and the thickness of the buried silicon oxide is 1.25μm, such as image 3 shown;

[0067] 2. Dry thermal oxidation generates a 180nm oxide layer, photolithography retains the oxide layer in the lead area, and removes the oxide layer in other areas;

[0068] 3. Dry thermal oxidation generates an oxide layer of 85nm, photolithography retains the oxide layer in the lead area, and removes the oxide layer in other areas;

[0069] 4. Dry thermal oxidation generates a 170nm oxide layer and removes all oxide layers;

[0070] 5. Dry thermal oxidation to generate a 100nm oxide layer, photolithography resistance pattern, BOE etching oxide layer, TMAH etching to buried silicon dioxide, forming resistance pattern;

[0071] 6. Dry thermal oxidation generates an oxide layer of 80nm, which protects the side of the resistor from the external environment, such as Figure 4 shown;

[0072] 7. Boron ion impl...

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Abstract

The invention relates to huge piezoresistive effect generated by interface trap action in nano scale and a method for manufacturing a nano huge piezoresistor, and belongs to the field of micro electromechanical systems. The huge piezoresistor is specifically characterized in that the thickness of the piezoresistor is nano-scale, and the piezoresistive effect comes from electron trap effect at the interface of silicon and silicon dioxide. The prior piezoresistive effect of the silicon comes from the change of mobility ratio of stressed current carriers, while the huge piezoresistance in the nano scale is generated by changing the concentration of the current carriers under the electron trap effect at the interface of the silicon and the silicon dioxide by the action of stress. Along with the reduction of the thickness of the piezoresistor, the interface effect accounts for larger proportion, and the piezoresistive effect generated by the interface trap is more obvious. The piezoresistor manufactured by the method has the advantages of large piezoresistive coefficient, same resistance value change of transverse piezoresistance and the longitudinal piezoresistance, and compatibility with a semiconductor process, and can be applied to sensors and micro electromechanical systems.

Description

technical field [0001] The invention relates to a giant piezoresistor produced by the action of interface traps at the nanometer scale and a manufacturing method of the nanometer giant piezoresistor, belonging to the field of micro-electromechanical systems. Background technique [0002] In 1954, American scientist Smith discovered the piezoresistive effect of semiconductor materials (C.S.Smith, "Piezoresistance Effect in Germanium and Silicon," Physical Review, vol.94, p.42, 1954.). Subsequently, scientists conducted in-depth research on the piezoresistive effect of silicon materials. Because silicon piezoresistive has the advantages of high piezoresistive coefficient and compatibility with semiconductor manufacturing, the piezoresistive effect of silicon material has been widely used as a detection method in sensors of MEMS, such as pressure sensors, acceleration sensors and various A biochemical sensor with a cantilever beam structure. [0003] Although the piezoresisti...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): B82B1/00B82B3/00G01L1/18G01P15/12H01L21/18
Inventor 杨永亮李昕欣
Owner SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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