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Apparatus for implementing 128 bit cipher key length AES algorithm by VLSI

A technology of key length and algorithm, applied in the field of information encryption, it can solve the problems of infrequent key changes and not suitable for power-sensitive applications, so as to solve the speed bottleneck, high flexibility and portability, and reduce the number of chips. area effect

Inactive Publication Date: 2010-12-08
SHANDONG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The existing VLSI circuits for the AES algorithm mostly focus on the consideration of the chip area, and there are deficiencies in the consideration of the power consumption. A Method for Realizing the AES Algorithm", which adopts the method of temporarily generating the round key in the iterative process. Although this method can save the area of ​​the on-chip memory, the key does not change frequently in most applications, and the same key needs to be used for multiple consecutive times. For encryption or decryption operations, frequent key expansion operations will bring additional dynamic power consumption, which is not suitable for applications that are sensitive to power consumption

Method used

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  • Apparatus for implementing 128 bit cipher key length AES algorithm by VLSI
  • Apparatus for implementing 128 bit cipher key length AES algorithm by VLSI
  • Apparatus for implementing 128 bit cipher key length AES algorithm by VLSI

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Experimental program
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Embodiment 1

[0071] Embodiment 1: (hardware embodiment)

[0072] Embodiment 1 of the present invention such as figure 1 As shown, it includes a microprocessor interface module 3, a key expansion module 1, an encryption operation module 5, a decryption operation module 4, a key round number selector 2, a data output selector 7 and a state output selector 6, and is characterized in that The microprocessor interface module 3 is connected with the microprocessor, and receives commands and data from the microprocessor; the microprocessor interface module 3 is respectively connected with the key expansion module 1, the encryption operation module 5, the decryption operation module 4, and the key wheel Number selector 2, data output selector 7 and state output selector 6 are connected to control the operation of key expansion module 1, encryption operation module 5 and decryption operation module 4, and are responsible for controlling key round number selector 2, The state output selector 6 and ...

Embodiment 2

[0076] Embodiment 2: (method embodiment)

[0077] The operation method of the microprocessor interface module in the above-mentioned device, such as figure 2 As shown, the steps are as follows:

[0078] 8: If a write data command is received, store the data in the internal data register;

[0079] 9: If the key expansion command is received, output the start signal to the key expansion module; output the control signal to the status output selector, and gate the status output of the key expansion module;

[0080] 10: If an encryption operation command is received, output the start signal to the encryption operation module; output the control signal to the key round number selector, and select the key round number output of the encryption operation module; output the control signal to the status output selector, and select Encryption operation module status output;

[0081] 11: If the decryption operation instruction is received, output the start signal to the decryption ope...

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Abstract

A device for advanced encryption standard (AES) algorithm with 128 bit key length by use of a very large scale integrated circuit (VLSI) belongs to the technical field of information encryption. The device comprises a microprocessor interface module, a key expansion module, an encryption operation module, a decryption operation module, a key round selector, a data output selector and a state output selector. The microprocessor interface module is connected with a microprocessor and receives the commands and the data from the microprocessor. The microprocessor interface module is also connected with the key expansion module, the encryption operation module, the decryption operation module, the key round selector, the data output selector and the state output selector, respectively, so as to control the operations of the key expansion module, the encryption operation module and the decryption operation module respectively and to control the key round selector, the data output selector and the state output selector to output the operation results to the external microprocessor. The device has the advantages of low power consumption, high operation efficiency and high flexibility and portability.

Description

technical field [0001] The invention relates to a device for realizing AES algorithm with 128-bit key length by using VLSI, which belongs to the technical field of information encryption. Background technique [0002] AES (Advanced Encryption Standard) is a new information encryption algorithm selected by the National Institute of Standards and Technology (NIST) in 2000 to replace the DES standard formulated in 1977. This algorithm will serve as a new data Encryption standards are used in various security fields. For example, the ieee802.11i standard approved in 2004 adopted the AES algorithm for the first time to solve the security problem of 802.11 wireless LAN. AES adopts the Rijndael algorithm, which is a symmetric key type encryption algorithm standard. It adopts an iterative block cipher algorithm, the block length is 128bit, and the key length can be set as 128bit, 192bit or 256bit. common. AES has high security performance. For the AES encryption algorithm with 128...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L9/14H04L9/32
Inventor 王祖强桑涛李运田李春蕾姜伟
Owner SHANDONG UNIV