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Modulated multi-die package construction and method thereof

A packaging method and packaging structure technology, which are applied in the manufacturing of electrical components, electrical solid-state devices, semiconductor/solid-state devices, etc., can solve problems such as inability to align, increase in resistance value, and affect die performance.

Active Publication Date: 2009-07-22
CHIPMOS TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The thinned die is redistributed on another substrate, and then multiple dies are formed into a package by injection molding; since the die is very thin, the package is also very thin, so when After the package is detached from the substrate, the stress of the package itself will cause the package to warp, increasing the difficulty of the subsequent cutting process
[0006] In addition, after the wafer is diced, when it is reconfigured on another substrate, because the size of the new substrate is larger than the original size, it will not be aligned in the subsequent ball planting process, and the reliability of the packaging structure will be reduced.
For this reason, the present invention provides a method to form an alignment mark (alignment mark) on the back of the wafer before wafer dicing, which can effectively solve the problems of inability to align and package warpage during ball planting.
[0007] In addition, during the entire packaging process, there will be a problem that when the ball is planted, the manufacturing equipment will exert local excessive pressure on the die, which may damage the die; at the same time, it may also be caused by the material of the ball. The resistance value between the pads on the pad becomes larger, which affects the performance of the grain and other issues

Method used

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  • Modulated multi-die package construction and method thereof
  • Modulated multi-die package construction and method thereof
  • Modulated multi-die package construction and method thereof

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Embodiment Construction

[0048] The direction discussed in the present invention is a chip reconfiguration packaging method, in which multiple chips are reconfigured on another substrate and then packaged. In order to provide a thorough understanding of the present invention, detailed steps and components thereof will be set forth in the following description. Obviously, the practice of the invention is not limited to specific details familiar to those skilled in the art of chip stacking. On the other hand, well-known chip formation methods and detailed steps of back-end processes such as chip thinning are not described in detail to avoid unnecessary limitations of the present invention. However, for the preferred embodiments of the present invention, it will be described in detail as follows, but in addition to these detailed descriptions, the present invention can also be widely implemented in other embodiments, and the scope of the present invention is not limited. Subsequent patent scope shall pr...

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Abstract

The invention relates to a modularized multi-crystal grain encapsulating structure, comprising; a plurality of crystal grains, an encapsulated body, a plurality of patterned metal line sections, a patterned protective layer, a plurality of conductive components and a heat radiator, wherein, each of the crystal grains is provided with an active surface on which a plurality of weld pads are provided; the encapsulated body circles and covers five surfaces of each crystal grain and exposes the active surface and each weld pad of each crystal grain; two ends of part of the patterned metal line sections are electrically connected with a plurality of weld pads on the active surfaces of the crystal grains, while one end of part of the patterned metal line sections are electrically connected with a plurality of weld pads on the active surfaces of the crystal grains; the patterned protective layer covers a plurality of patterned metal line sections and exposes the other ends of part of the patterned metal line sections; the conductive components are electrically connected with the other end of each exposed patterned metal line section and the heat radiator is formed at the back of the encapsulated body.

Description

technical field [0001] The invention relates to a semiconductor packaging method, in particular to a packaging method for reconfiguring crystal grains of different sizes and functions. Background technique [0002] Semiconductor technology has developed quite rapidly, so the miniaturized semiconductor die (Dice) must have diversified functional requirements, so that the semiconductor die must be configured with more input / output pads ( I / O pads), thus making the density of metal pins (pins) also increase rapidly. Therefore, the early lead frame packaging technology is no longer suitable for high-density metal pins; therefore, a ball grid array (BGA) packaging technology has been developed. The ball array package has the advantage of higher density than the lead frame package. In addition, its solder balls are less prone to damage and deformation. [0003] With the popularity of 3C products, such as: cell phone (Cell Phone), personal digital assistant (PDA) or iPod, etc., i...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/50H01L21/56H01L21/60H01L25/075H01L25/00H01L25/18H01L23/48H01L23/31H01L23/34
CPCH01L2224/24137H01L24/19H01L24/96H01L24/20H01L21/568H01L2224/12105H01L2224/19H01L2224/20H01L2224/73267H01L2924/3511
Inventor 傅文勇
Owner CHIPMOS TECH INC
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