Delay-locked loop and a stabilizing method thereof

Abstract

A delay-locked loop includes a phase detector, a shift register, a digital low pass filter, a digital to analog converter, a bias circuit, and a delay circuit. The phase detector generates a lagging signal and a leading signal corresponding to a phase difference between an input clock signal and a feedback clock signal. The shift register outputs a digital data according to the lagging signal and the leading signal. The digital low pass filter generates a selecting signal according to the digital data. The bias circuit generates a first control voltage and a second control voltage in response to the bias voltage converted from the selecting signal. The delay circuit generates the feedback clock signal corresponding to the first control voltage and the second control voltage.

Description

technical field [0001] The present invention relates to a delay-locked loop, in particular to a delay-locked loop including a digital circuit. Background technique [0002] With the advancement of semiconductor technology, the operating frequency of VLSI circuits has increased significantly. Therefore, electronic equipment needs to upgrade its operating frequency to keep up with the ever-advancing semiconductor process. For example, ultra-high-speed system circuits, such as wireless handsets, fiber optic links, microprocessors, and system-on-chips (SoCs), have all reached GHz levels. [0003] Since many circuits need to be integrated into one chip, the clock signal needs to be widely distributed throughout the chip, which will cause clock skew. For example, when an input clock signal drives the chip, due to the different lengths of the paths passed by the internal clock signal of the chip, there will be an uncertain gap between the input clock signal and the internal clock...

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Problems solved by technology

[0007] However, in this traditional delay-locked loop, the control voltage VCTL cannot keep up with the fast-changing hysteresis signal UP and the leading signal DN output by the phase detector, so that the voltage-controlled delay line 107 cannot generate the correct delay time, so it cannot be locked correctly clock signal, causing circuit instability on the chip

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