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Storage element and manufacturing method thereof

A storage element and manufacturing method technology, applied in semiconductor/solid-state device manufacturing, electrical components, semiconductor devices, etc., can solve problems such as difficulty in charge entry, affecting charge storage capacity, and affecting component performance, so as to avoid oxide invasion and improve Data retention ability, effect of avoiding silicon loss

Inactive Publication Date: 2009-08-19
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The expansion of the first oxide layer 102a in the edge region makes it difficult for charges to enter the nitride layer 102b, thereby affecting device performance
Specifically, the erase efficiency (Erase Efficiency) of the component will decline (Degrade) after repeated endurance cycle voltage (Endurance Cycling) tests, which will affect the ability to store charges

Method used

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  • Storage element and manufacturing method thereof
  • Storage element and manufacturing method thereof
  • Storage element and manufacturing method thereof

Examples

Experimental program
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Effect test

no. 1 example

[0043] Figure 2A to Figure 2B It is a cross-sectional view of the manufacturing process of the storage body element in this embodiment.

[0044] Please refer to Figure 2A Firstly, a charge storage structure 202 is formed on the substrate 200 . Next, a gate conductor layer 204 and a top cover layer 206 are sequentially formed on the charge storage structure 202 , and then a photoresist layer 208 is formed on the top cover layer 206 .

[0045] In one embodiment, the material of the substrate 200 is, for example, a bulk substrate. In another embodiment, the material of the substrate 200 may be a silicon on insulator (Silicon On Insulator, SOI for short) substrate. In one embodiment, the charge storage structure 202 is composed of a double-layer structure of a gate dielectric layer structure 202a and a charge trapping layer 202b. The gate dielectric layer structure 202a includes a first oxide layer such as a silicon oxide layer. The material of the charge trapping layer 202...

no. 2 example

[0051] Figures 3A to 3B It is a cross-sectional view of a part of the manufacturing process of the storage body device according to the second embodiment of the present invention.

[0052] Please refer to Figures 3A to 3B , the second embodiment of the present invention is similar to the first embodiment, but the etching process P1 of the first embodiment is changed to the etching process P2. In the etching process P1 of the first embodiment, the substrate 200 is used as the etching stop layer, while in the second embodiment of the present invention, the gate dielectric layer structure 202a is used as the etching stop layer.

[0053] Please refer to Figure 3A Firstly, a charge storage structure 202 is formed on the substrate 200, and the charge storage structure 202 includes a gate dielectric layer structure 202a, a charge trapping layer 202b and a second oxide layer 202c. Next, a gate conductor layer 204 and a top cover layer 206 are sequentially formed on the charge st...

no. 3 example

[0057] Figure 4A to Figure 4C It is a cross-sectional view of the manufacturing process of the storage body element part according to the third embodiment of the present invention.

[0058] Please refer to Figure 4A Firstly, a charge storage structure 202 is formed on the substrate 200, and the charge storage structure 202 includes a gate dielectric layer structure 202a, a charge trapping layer 202b and a second oxide layer 202c. Then, a gate conductor layer 204 and a top cover layer 206 are sequentially formed on the second oxide layer 202 c , and then a photoresist layer 208 is formed on the top cover layer 206 . This part of the process can be completed in the same way as in the first embodiment.

[0059] Please refer to Figure 4B , performing a patterning process, using the photoresist layer 208 as a mask, and the second oxide layer 202c as a stop layer, to pattern the top cap layer 206 and the gate conductor layer 204 . For example, hydrogen bromide, helium, a mixe...

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Abstract

The invention discloses a manufacture method of a storage element, which includes the steps that charge storage structures with grid dielectric layer structure are formed on a substrate in sequence and then a grid conductor layer is formed above the charge storage structure. Then, the grid conductor layer and at least part of the charge storage structures are patterned. The sectional plane of the patterned charge storage structures takes the shape of a trapezoid or a quasi trapezoid. The edge of the trapezoid or the quasi trapezoid, which is close to the grid conductor layer, is a short edge, and the edge thereof which is close to the substrate, is a long edge.

Description

technical field [0001] The present invention relates to a structure of a semiconductor element and a manufacturing method thereof, and in particular to a structure of a storage element and a manufacturing method thereof. Background technique [0002] The charge trap memory element is a new type of nonvolatile memory. It uses a charge trapping layer such as silicon nitride to replace the polysilicon floating gate layer in the traditional flash memory device. Since the material of the charge trapping layer has the characteristic of trapping electrons, the electrons injected into the charge trapping layer are not evenly distributed throughout the charge trapping layer, but are concentrated in a local area of ​​the charge trapping layer in a Gaussian distribution. . Since the electrons injected into the charge trapping layer are only concentrated in a local area, the sensitivity to the defects of the tunneling oxide layer is relatively small, and the leakage current of the dev...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/28H01L21/336H01L29/423H01L29/792
Inventor 陈致霖刘光文陈昕辉
Owner MACRONIX INT CO LTD
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