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Clock data recovery device

A clock data recovery and clock signal technology, applied in the direction of synchronization device, digital transmission system, automatic power control, etc., can solve the problems of changing data transition time, unable to recover clock signal and data, etc., and achieve the effect of stable recovery

Active Publication Date: 2013-05-22
THINE ELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] However, the data transition timing of the input digital signal fluctuates due to transmitter clock jitter generated by power supply voltage fluctuations and other noises in the transmitter that sends out the digital signal; The data transition timing of the digital signal also fluctuates due to intersymbol interference, etc., which is generated due to a mixture of irregular data patterns in the digital signal and attenuation in the transmission path
When the clock jitter or intersymbol interference of these transmitters is large, the above-mentioned existing devices sometimes cannot recover the clock signal and data

Method used

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no. 1 Embodiment approach

[0055] Next, a first embodiment of the clock data recovery device of the present invention will be described. Figure 4 It is a diagram showing the timing of sampling the data of the digital signal in the first embodiment. This figure schematically shows an eye diagram of a digital signal, and also shows the timing of data sampling using CKX and CK. The clock data recovery device 1 of the present embodiment indicates the timing of sampling with the clock signal CK during the data stabilization period for the first signal and the second signal to which the offset (±Voff) is given to the digital signal, and When the data transitions, the clock signal CKX is used to indicate the timing of sampling.

[0056] The two signals of the clock signal CK and the clock signal CKX have the same period T. The sampling time t indicated by the clock signal CK C , and the sampling instant t indicated by the clock signal CKX X have "t X -t C =T / 2". In addition, in each nth period T(n) of t...

no. 2 Embodiment approach

[0096] Next, a second embodiment of the clock data recovery device of the present invention will be described. Figure 15 The overall schematic configuration of the clock data recovery device 2 of the second embodiment is shown. and Figure 5 Compared with the configuration of the clock data recovery device 1 of the first embodiment shown, the Figure 15 The clock data recovery device 2 of the second embodiment shown is different in that it has an offset specifying unit 30A instead of the offset specifying unit 30 .

[0097] The offset determination unit 30A inputs the digital value D(n) and the digital value DX(n) output from the detection unit 20 in each period T(n). Then, the offset determining section 30A determines the offset imparting amount in the sampling section 10 so that the time indicated by the clock signal CKX becomes the center of the transition time distribution of the first signal value when the value D(n-1) is at a high level, And when the value D(n-1) is ...

no. 3 Embodiment approach

[0110] Next, a third embodiment of the clock data recovery device of the present invention will be described. Figure 18 It is a figure which shows the whole schematic structure of the clock data restoration apparatus 3 of 3rd Embodiment. and Figure 15 Compared with the configuration of the clock data recovery device 2 of the second embodiment shown, the Figure 18 The clock data recovery device 3 of the third embodiment shown is different in that it has an offset specifying unit 30B instead of the offset specifying unit 30A.

[0111] The offset determination unit 30B inputs the digital value D(n) and the digital value DX(n) output from the detection unit 20 in each period T(n). Further, the offset determination section 30B determines the offset imparting amount in the sampling section 10 so that the time indicated by the clock signal CKX when the value D(n-1) is at a high level is the center of the transition time distribution of the first signal value, And when the value...

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Abstract

A clock / data recovery device 1 comprises a sampler 10, a detector 20, an offset determination part 30, a clock output part 40, and a DA converter 50. The phases of clock signals CK and CKX are adjusted so as to match with the phase of an input digital signal. An offset amount (±Voff) added in the sampler 10 is adjusted so as to match with a peak time of a data transition time distribution of a first signal in a case where a value D(n-1) is HIGH level, and is adjusted so as to match with a peak time of a data transition time distribution of a second signal in a case where the value D(n-1) is LOW level. Either of the clock signals CK and CKX is outputted as the recovered clock signal. Time series data of a digital value D(n) is outputted as the recovered data.

Description

technical field [0001] The present invention relates to a device for recovering a clock signal and data from an input digital signal. Background technique [0002] Since the waveform of a digital signal output from a transmitter is degraded while being transmitted from the transmitter to a receiver via a transmission path, it is necessary to restore a clock signal and data on the receiver side. Such a clock data recovery device for recovery is disclosed in Patent Documents 1 and 2, for example. [0003] In the devices disclosed in these documents, each bit of data is detected at three timings in consideration of fluctuations in timing of data transitions in digital signals with degraded waveforms. At this time, among the three timings when detecting each bit of data, the first timing is set near the initial time of the data stable period of the bit, and the second timing is set near the expiration time of the data stable period of the bit. , the third timing is set at an i...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L25/03H03L7/08H03L7/081H04L7/02
CPCH03L7/07H03L7/091H04L7/033H03L7/081H04L25/03H03L7/08H04L7/02
Inventor 小沢诚一
Owner THINE ELECTRONICS