Manufacturing method of semiconductor device

Abstract

The invention provides a manufacturing method of a semiconductor device. The method includes the steps: respectively forming a first gate insulation layer and a second gate insulation layer on a base plate; roundly forming a gate layer; removing part of the gate layer, the first gate insulation layer and part of the second gate insulation layer to form a first gate, a first residual gate insulation layer, a second gate and a second residual gate insulation layer, wherein the first residual gate insulation layer which is not covered by the first gate is provided with a first thickness, the second residual gate insulation which is not covered by the second gate is provided with a second thickness, and the ratio of the first thickness and the second thickness is between 1:10 and 1:20; and respectively forming a pair of first gap walls and a pair of second gap walls on the side walls of the first gate and the second gate. The invention can avoid the problems of poor electric property or lowered reliability of an assembly, save the amount of masks used by the process and lower the process cost.

Description

technical field [0001] The present invention relates to a manufacturing method of a semiconductor device, in particular to a process for integrating a semiconductor device including a plurality of components with different gate insulating layer thicknesses. Background technique [0002] With the continuous advancement of semiconductor process shrink technology, and the stringent requirements for size and function of portable and consumer products, System on a Chip (SoC) has become the mainstream trend of integrated circuit design in the electronics industry. In one SoC, logic components, memory components, analog components and various input / output (I / O) interfaces are provided, so one chip has complete system operation functions. For example, a liquid crystal display chip needs to be driven by a high voltage metal oxide semiconductor transistor (HVMOS) driven by a high voltage (such as 30V or 40V), and driven by a low or medium voltage (such as 2.5V or 5V). ) logic circuit...

AI Technical Summary

Problems solved by technology

In the known semiconductor process, after forming the gate, for components with different thicknesses of the gate insulating layer, a full-scale etching method can be used to remove the remaining gate insulating layer, but due to the The thickness difference of the remaining gate insulation layer is still too large, which will cause unwanted substrate loss or gate defects, resulting in poor electrical performance and reduced reliability of the component

However, the method of increasing the number of masks to remove the remaining gate insulating layer located in different component regions will increase the manufacturing cost

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