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Insulated gate semiconductor device

An insulated gate type, n-type semiconductor technology, used in semiconductor devices, semiconductor/solid-state device components, electric solid-state devices, etc., can solve the problems of reducing the area of ​​​​the action area, expanding the chip size, and increasing the area occupied by the protection diode. The effect of reducing the occupied area

Inactive Publication Date: 2009-11-11
SANYO ELECTRIC CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, when a part or all of the junction area of ​​a plurality of concentric pn junctions is increased, the area occupied by the protection diode on the chip increases.
[0009] Therefore, when compared with the same chip size, the area of ​​the operating region is reduced and the on-resistance of the MOSFET is increased
Or, if the area of ​​the same operating region is secured, there is a problem of increasing the chip size

Method used

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Examples

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Embodiment Construction

[0064] refer to Figure 1 to Figure 19 , the embodiment of the present invention will be described by taking the case where a transistor unit of a MOSFET is provided in an operating region as an example.

[0065] First, refer to Figure 1 to Figure 8 The first embodiment will be described. figure 1 It is a plan view showing the MOSFET of this embodiment.

[0066] The MOSFET has a gate electrode 1 , a protection diode group 2 and an operating region 5 .

[0067] A plurality of MOS transistor cells 6 are arranged in the operating region 5 . Hereinafter, the operating region 5 refers to a region where the MOS transistor unit 6 is arranged. The gate pad electrode 1 is arranged, for example, outside the operating region 5 , and is connected to the gate electrode of each MOS transistor cell 6 via a gate connection electrode 4 arranged around the operating region 5 .

[0068] The MOS transistor cell in the operating region 5 has a known structure, so it is omitted from the illust...

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Abstract

The invention provides an insulated gate semiconductor device. The protective diode in prior art is made by forming a concentric circle by a plurality of PN junctions with different diameter, and is configured underneath with a dimension substantially the same with the gate pad electrode. A method of increasing total area of the PN junction composing the protective diode is known as a method for enhancing ESD capacity of the MOSFET. A problem of occupation area increment of the protective diode on the cip is in presence when increasing a part or all of the junction area of a plurality of PN junctions forming a concentric circle. In the insulated gate semiconductor device, a plurality of protective diodes are arranged as a protective diode group in parallel connect, and average value of the total junction area of the protective diode group is set to a value capable of ensuring the expected electrostatic discharging capacity. By keeping the total junction area average value equal to the junction area average value of structure in prior art, ESD tolerance is made equal to a conventional ESD tolerance, and occupation area of the protective diode group on the chip is reduced.

Description

technical field [0001] The invention relates to an insulated gate type semiconductor device, in particular to an insulated gate type semiconductor device with improved electrostatic discharge capacity. Background technique [0002] In existing insulated gate semiconductor devices such as MOSFET (Metal Oxide Semiconductor Field Effect Transistor: Metal Oxide Semiconductor Field Effect Transistor), in order to protect the thin gate insulating film (oxide film) from electrostatic discharge (electrostatic discharge: the following Influenced by ESD), a protection diode is connected between the gate electrode and the source electrode, and a protection resistor is connected to the gate electrode. [0003] Figure 20 is a plan view showing a conventional MOSFET. [0004] A plurality of MOSFET cells 36 are arranged in the operating region 35 , and the gate electrode of each cell 36 is drawn out of the operating region 35 through the gate connection electrode 34 and connected to the ...

Claims

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Application Information

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IPC IPC(8): H01L27/06H01L23/60H01L29/06H01L29/861H01L29/78
CPCH01L29/7808H01L29/0696H01L27/0255H01L29/0692H01L29/4238H01L2924/0002H01L2924/00
Inventor 矢岛学
Owner SANYO ELECTRIC CO LTD
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