Method for etching opening in laminated dielectric layer

Abstract

A method for etching an opening in laminated dielectric layers comprises: providing a substrate with laminated dielectric layers; forming a photoetching adhesive layer on the laminated dielectric layers, imaging the photoetching adhesive layer to form an opening pattern; etching the laminate dielectric layers at the bottom of the opening pattern and not stopping until the downmost layer in the laminate dielectric layers is exposed; removing the photoetching adhesive layer; etching the downmost layer in the laminated dielectric layers at the bottom of the opening pattern; forming an opening penetrating through the laminate dielectric layer; wherein, in the step of etching the downmost layer in the laminate dielectric layer at the bottom of the opening pattern, etching is carried out by inductive coupling of plasma body. The invention can reduce the damage on the opening side wall when the opening is etched in the laminated dielectric layer.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for etching openings in stacked dielectric layers. Background technique [0002] With the development of semiconductor integrated circuit manufacturing technology, higher and higher integration is required, and the requirements for line width and process are becoming more and more stringent. While moving towards a smaller line width technology node, the IC industry uses copper and low dielectric constant materials to form the interconnection structure of the back stage to reduce the interconnect resistance capacitance (RC) delay. Compared with the process of forming aluminum interconnection lines by etching aluminum in the aluminum metal process, copper needs to be formed by a dual damascene process due to its characteristics of easy diffusion and difficult etching. The intermediate dielectric layer is etched with trenches and vias, and then copper i...

AI Technical Summary

Problems solved by technology

The hardness of the intermediate dielectric layer of the material is relatively small. After the connection hole is etched, the etch stop layer at the bottom of the connection hole needs to be removed by further etching, and the etching in this step will damage the material of the intermediate dielectric layer, resulting in the formed connection The profile of the side wall of the hole becomes poor, which in turn affects the deterioration of the formed copper interconnection structure and affects the electrical properties of the formed device

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