Method for etching opening in laminated dielectric layer

A dielectric layer and intermetallic dielectric layer technology, which is applied in the direction of electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve the problem of poor profile of the side wall of the connection hole, poor copper interconnect structure characteristics, and damage to the material of the intermediate dielectric layer and other problems, to achieve the effect of improving rounding defects, reducing etching damage, and strong directionality

Inactive Publication Date: 2009-12-02
SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The hardness of the intermediate dielectric layer of the material is relatively small. After the connection hole is etched, the etch stop layer at the bottom of the connection hole needs to be removed by further etching, and the etching in this step will damage the material

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  • Method for etching opening in laminated dielectric layer
  • Method for etching opening in laminated dielectric layer
  • Method for etching opening in laminated dielectric layer

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Embodiment Construction

[0022] The specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0023] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, the present invention can be implemented in many other ways different from those described here, and those skilled in the art can make similar extensions without violating the connotation of the present invention, so the present invention is not limited by the specific implementations disclosed below.

[0024] Secondly, the present invention is described in detail using schematic diagrams. When describing the embodiments of the present invention in detail, for the convenience of explanation, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic diagram is only an example, and it should not be limited here. ...

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Abstract

A method for etching an opening in laminated dielectric layers comprises: providing a substrate with laminated dielectric layers; forming a photoetching adhesive layer on the laminated dielectric layers, imaging the photoetching adhesive layer to form an opening pattern; etching the laminate dielectric layers at the bottom of the opening pattern and not stopping until the downmost layer in the laminate dielectric layers is exposed; removing the photoetching adhesive layer; etching the downmost layer in the laminated dielectric layers at the bottom of the opening pattern; forming an opening penetrating through the laminate dielectric layer; wherein, in the step of etching the downmost layer in the laminate dielectric layer at the bottom of the opening pattern, etching is carried out by inductive coupling of plasma body. The invention can reduce the damage on the opening side wall when the opening is etched in the laminated dielectric layer.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for etching openings in stacked dielectric layers. Background technique [0002] With the development of semiconductor integrated circuit manufacturing technology, higher and higher integration is required, and the requirements for line width and process are becoming more and more stringent. While moving towards a smaller line width technology node, the IC industry uses copper and low dielectric constant materials to form the interconnection structure of the back stage to reduce the interconnect resistance capacitance (RC) delay. Compared with the process of forming aluminum interconnection lines by etching aluminum in the aluminum metal process, copper needs to be formed by a dual damascene process due to its characteristics of easy diffusion and difficult etching. The intermediate dielectric layer is etched with trenches and vias, and then copper i...

Claims

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Application Information

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IPC IPC(8): H01L21/768H01L21/311
Inventor 尹晓明张世谋沈满华孙武
Owner SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP
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