Method, device and system for processing multiple interrupt types

A technology of a processing device and a processing method, which is applied in the computer field, can solve problems such as low CPU efficiency and low CPU concurrent processing capability, and achieve the effects of improving efficiency, saving CPU processing time, and avoiding mutually exclusive operations

Inactive Publication Date: 2010-01-27
HUAWEI DIGITAL TECH (CHENGDU) CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] The inventor found in the process of realizing the present invention: in the above-mentioned technology, the CPU needs to judge the interrupt type of the interrupt request before processing the interrupt request, and because in the interrupt

Method used

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  • Method, device and system for processing multiple interrupt types
  • Method, device and system for processing multiple interrupt types
  • Method, device and system for processing multiple interrupt types

Examples

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Embodiment 1

[0030] Embodiment one, such as figure 1 As shown, a multi-interrupt processing method provided by an embodiment of the present invention may include the following steps:

[0031] Step 101: receiving an interrupt request;

[0032] Step 102: Obtain the interrupt type of the above interrupt request;

[0033] The interrupt types of the interrupt requests obtained above can be: read requests, write requests, other requests other than read and write and exception requests, exception requests, etc.; of course, other methods can also be used for the classification of interrupt request types, which do not affect the present invention implementation of the embodiment. The interrupt type of the interrupt request can be represented by the interrupt number, and the interrupt type of the interrupt request can be obtained as follows: the interrupt number of the interrupt request is obtained.

[0034] Step 103: Send the above interrupt request to the interrupt queue corresponding to the ab...

Embodiment 2

[0049] Embodiment 2. In this embodiment, the network card receives an interrupt request and then sends it to a multi-core CPU as an example for illustration. It can be understood that the network card is only an example of an I / O device, and the I / O device can also be other devices other than the network card, such as a keyboard, etc. figure 2 It is a schematic diagram of the system structure of the embodiment of the present invention, including: a network card 201, wherein there are multiple interrupt queues 201A in the network card 201, and the number of interrupt queues 201A can be determined by the number of interrupt types. In this embodiment, the interrupt types are: read request, Write request, abnormal request, read and write request and other requests other than abnormal request, these four types are illustrated as examples; fast peripheral interconnection bus switch 202 connects network card 201 and Northbridge 203, Northbridge 203 and multiple central processing uni...

Embodiment 3

[0054] Embodiment three, such as image 3 As shown, the embodiment of the present invention also provides a multi-interrupt processing device, including:

[0055] an interrupt receiving unit 301, configured to receive an interrupt request;

[0056] A type obtaining unit 302, configured to obtain the interrupt type of the received interrupt request;

[0057] A queue selection sending unit 303, configured to send the above interrupt request to the interrupt queue corresponding to the above interrupt type;

[0058] The CPU selects the sending unit 304, configured to send the interrupt request in the above interrupt queue to the CPU core bound to the above interrupt queue.

[0059] Optionally, each interrupt queue has a corresponding interrupt queue number;

[0060] The above-mentioned queue selection sending unit 303 is specifically configured to send the interrupt request to an interrupt queue of a certain interrupt number corresponding to the above-mentioned interrupt type. ...

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PUM

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Abstract

The invention discloses a method, a device and a system for processing multiple interrupt types. The method comprises the following steps: receiving interrupt requests and obtaining the interrupt types of the interrupt requests; sending the interrupt requests to an interruption queue which corresponds to the interrupt types; and sending the interrupt requests in the interruption queue to a central processing unit (CPU) core bound to the interruption queue. In the technical scheme, the interrupt types of the interrupt requests are identified before the interrupt requests enter the interruption queue, and then the interrupt requests are sent to the interruption queue which corresponds to the interrupt types. The interrupt requests in the interruption queue have the same types, therefore, the CPU core does not need to judge the interrupt types before processing the interrupt requests so as to save the processing time of the CPU and enhance the efficiency of the CPU. In addition, one CPU processes one type of interrupt requests so as to avoid the mutually exclusive operation among the CPU cores, improve the concurrent processing performance of the CPU and enhance the efficiency of the CPU.

Description

technical field [0001] The present invention relates to the field of computer technology, in particular to a processing method, device and system of multiple interrupt types. Background technique [0002] In a computer system, an input / output (Input / Output, I / O) device uses an interrupt signal to notify a host of various events, such as a sending or receiving request, sending or receiving completion, and the like. The above-mentioned host may be any computer, server and other equipment with a central processing unit (Central Processing Unit, CPU). The interrupt has a high priority in the operating system, which requires the program to immediately stop the executing task to handle the interrupt. The aforementioned interrupt signal may be an interrupt request with a set interrupt number. [0003] For the computer system, among the interrupt requests between I / O devices, read and write requests have the largest proportion, and the processing performance requirements for the r...

Claims

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Application Information

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IPC IPC(8): G06F13/24
Inventor 张巍
Owner HUAWEI DIGITAL TECH (CHENGDU) CO LTD
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