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High-speed serial buss system capable of being dynamically reconfigured and control method thereof

A high-speed serial bus and bus technology, applied to instruments, electrical digital data processing, etc., can solve the problems of adding routing equipment, increasing system complexity, and failing to solve single-point failure failures, so as to improve reliability and improve operating efficiency Effect

Active Publication Date: 2010-03-03
CAPITAL NORMAL UNIVERSITY
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] 2) Bus communication cannot be dynamically reconfigured, that is, the link cannot be configured in real time according to the line connection status during system operation
After the parallel bus is powered on and configured, the link signal configuration becomes a fixed configuration, does not support the access of new nodes, and the node fails when there is a problem with the node line; the variable configuration of the serial bus for the link signal is static configuration, and the device After the manufacturing is completed (or started to operate), the link signal configuration becomes a fixed configuration, which cannot support fault tolerance for link signal failures, and does not solve the single point failure failure problem of traditional parallel bus storage
[0008] 3) The general-purpose bus does not meet the application requirements for the miniaturization of redundant fault-tolerant computers
The universal parallel bus has many connection lines, and the bus contains multiple data lines and address lines, which is difficult to miniaturize; the universal low-speed serial bus supports multiple communication nodes, but the speed is low, and it is not suitable for the internal communication of redundant fault-tolerant computers; the universal high-speed serial bus The row bus does not support multi-communication nodes, and expansion needs to increase routing equipment, which increases the complexity of the system and is difficult to meet the needs of system miniaturization

Method used

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  • High-speed serial buss system capable of being dynamically reconfigured and control method thereof
  • High-speed serial buss system capable of being dynamically reconfigured and control method thereof
  • High-speed serial buss system capable of being dynamically reconfigured and control method thereof

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Embodiment Construction

[0031] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0032] figure 1 It is the position of the bus system in the computer system according to the present invention. The bus system S103 establishes a communication link between the computer core CPU module S101 and a variety of peripherals S102. The bus system S103 is composed of three parts: the master node S104, the slave node S105 and the public transmission line S106. The computer core CPU module S101 is connected to the master control node S104 in the bus system S103; and each peripheral S102 is connected to each slave node S105.

[0033] figure 2 It is the network topology according to the embodiment of the present invention. The embodiment of the present invention uses a bus topology to connect each node, that is, the bus is composed of m bus lines S202 and two bus terminals S201, and the master node S104 and each slave node S105 are respec...

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Abstract

The invention discloses a high-speed serial buss system capable of being dynamically reconfigured based on lines and a realize method thereof. The buss comprises a plurality of communication lines; node equipment connected with the buss comprises one or a plurality of main control node(s) and a plurality of subsidiary nodes, wherein only the main control node(s) can start buss communication process; the node equipment is wholly or partially physically connected with the communication lines; the main control node(s) and the each subsidiary node adopt a semiduplex serial buss topological structure to realize physical connection; the main control node(s) and the subsidiary nodes respectively at least comprises a line detection module and a data dynamic reconfiguration module; the line detection module of the main control node(s) and the line detection module of the subsidiary nodes can immediately detect the connection status between the main node(s) and the subsidiary nodes according toinformation words between the two modules; and the data dynamic reconfiguration modules in the main control node(s) and the subsidiary nodes ensure the distribution method of data frame on the buss according to the ensured buss connection status.

Description

Technical field [0001] The invention relates to a computer bus structure and method, in particular to a dynamically reconfigurable high-speed serial bus structure and method. Background technique [0002] At present, the known computer bus structure can be divided into two categories, one is a parallel bus structure, and the other is a serial bus structure. [0003] Commonly used parallel bus structures such as PCI (CPCI), VXI, VME, EISA, MULTIBUS, etc., can be divided into three components: control signal, data signal and address signal. It has the advantages of convenient addressing, multi-space division, and strong expansion capability. Through the parallel mode, multiple data bytes can be transmitted in parallel in one access cycle, thereby using lower signal frequency to achieve high-speed data transmission. When a higher data transmission rate is required, the goal is achieved by expanding the data parallelism and increasing the signal transmission frequency. [0004] Commonl...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/40
Inventor 张伟功丁瑞关永尚媛园胡永勤周全张永祥
Owner CAPITAL NORMAL UNIVERSITY
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