Dual-port static random access memory unit

Abstract

The invention discloses a dual-port static random access memory unit comprising a write circuit, a data storage circuit and a read circuit. The write circuit is provided with two PMOS transistor usedas transmission gates and is used for writing input data signals from a bit line according to the control signals of the bit line; the data storage circuit comprises four transistors, forms a latch circuit through two phase inverters and is used for storing input data signals from the outside according to the write circuit; and the reading circuit comprises two NMOS transistors and is used for reading the input data signals stored by the data storage circuit according to the selected control signals. The read operation position and the write operation position of the dual-port static random access memory unit are separated from each other, thus the dual-port static random access memory unit can read and write data without interference and can work at high speed.

Description

technical field [0001] The invention relates to the technical field of semiconductor memory, in particular to a dual-port static random access memory (SRAM) unit, and more specifically, to an eight-transistor dual-port SRAM unit. Background technique [0002] In general, data storage in SRAM does not require additional refreshing like dynamic random access memory (DRAM), because SRAM uses latch-type cells. A one-port SRAM generally composed of six transistors is used as a unit circuit. [0003] figure 1 is the circuit diagram of a six-transistor single-port SRAM cell, figure 2 An existing dual port static memory cell is illustrated. [0004] refer to figure 1 , the six-tube single-port SRAM unit includes: two write transistors N03 and N04, N03 is connected to the bit line (BL) and the storage node na, N04 is connected to the supplementary bit line (BLB) and the storage node nb, the transistors N03 and N04 The switching state depends on the control signal on the word li...

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Problems solved by technology

[0012] figure 1 One disadvantage of the six-transistor single-port SRAM cell shown is that the write operation and the read data cannot be performed simultaneously

[0013] because figure 2 The dual-port static memory cell shown does not use a pair of bit lines but only one bit line, and the differential amplifier cannot be used in the read operation, so there will be a problem of long read operation time

Moreover, the disadvantage of the existing dual-port static memory cell is that during the write operation, a boosted voltage higher than the power supply voltage VDD needs to be applied to the word line (WL), so that the data can be written accurately. storage node

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