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Fabrication method of self-aligned tunneling field effect transistor

A tunneling field effect and transistor technology, applied in the field of microelectronics, can solve the problems that cannot be applied, reduce the shrinkability of tunneling field effect transistors, reduce the performance of tunneling field effect transistors, etc., and achieve the effect of simple process

Inactive Publication Date: 2011-12-07
FUDAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, since the doping of the source and drain of the tunneling field effect transistor is inverse to each other, the self-aligned source-drain formation process in the traditional MOS device cannot be applied, which greatly reduces the scalability of the tunneling field effect transistor. also degrades the performance of Tunneling Field Effect Transistors

Method used

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  • Fabrication method of self-aligned tunneling field effect transistor
  • Fabrication method of self-aligned tunneling field effect transistor
  • Fabrication method of self-aligned tunneling field effect transistor

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Experimental program
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Embodiment 1

[0046] Step 1: Please refer to figure 1 , a semiconductor integrated circuit substrate is provided, 100 is a wafer, and a layer of SiO has been covered on 100 2 or gate oxide layers of other dielectric materials, and 101a and 101b are isolation trench dielectric layers. Wafer 100 may be a silicon wafer, silicon-on-insulator, or other semiconductor material. The semiconductor substrate material of the wafer 100 can be n-type doped, p-type doped, or undoped (intrinsic semiconductor).

[0047] Step 2: Please refer to figure 2 , deposit film 201, film 202, film 203 and film 204 sequentially on the provided substrate, and then use photolithography and etching techniques to form opening 301 and opening in film 201, film 202, film 203 and film 204 302 , the thin film 201 is silicon dioxide or a high-K dielectric layer, and the thin film 202 is a conductive layer such as highly doped polysilicon, a metal layer or a combination thereof. The thin film 203 is a hard mask layer, whic...

Embodiment 2

[0055] Step 1: Please refer to figure 1 , a semiconductor integrated circuit substrate is provided, 100 is a wafer, and a layer of SiO has been covered on 100 2 or gate oxide layers of other dielectric materials, and 101a and 101b are isolation trench dielectric layers. Wafer 100 may be a silicon wafer, silicon-on-insulator, or other semiconductor material. The semiconductor substrate material of the wafer 100 can be n-type doped, p-type doped, or undoped (intrinsic semiconductor)

[0056] Step 2: Please refer to figure 2 , deposit film 201, film 202, film 203 and film 204 sequentially on the provided substrate, and then use photolithography and etching techniques to form opening 301 and opening in film 201, film 202, film 203 and film 204 302 , the thin film 201 is silicon dioxide or a high-K dielectric layer, and the thin film 202 is a conductive layer such as highly doped polysilicon, a metal layer or a combination thereof. The thin film 203 is a hard mask layer, which...

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Abstract

The invention belongs to the technical field of microelectronics, and specifically discloses a preparation method of a tunneling field effect transistor (TFET). The present invention uses a self-aligned process to form a tunneling field effect transistor. The preparation method of the tunneling field effect transistor is simple, the process of forming the tunneling field effect transistor has self-alignment characteristics, and the formation process of the source and the drain can be separated, so that it can be easily formed. Source structure different from substrate material.

Description

technical field [0001] The invention belongs to the technical field of microelectronics, in particular to a semiconductor device, in particular to a preparation method of a tunneling field effect transistor (TFET). Background technique [0002] In recent years, microelectronics technology with silicon integrated circuits as the core has developed rapidly. The development of integrated circuit chips basically follows Moore's law, that is, the integration level of semiconductor chips doubles every 18 months. Over the past period of time, the advancement of microelectronics technology has been based on the continuous optimization of the cost-effectiveness of materials, processes and processes. However, as noted in the International Technology Roadmap for Semiconductors (ITRS), scaling conventional CMOS transistors has become increasingly difficult for 45nm and finer processes. The short-channel effect, common to all standard metal-oxide-semiconductor field-effect transistors (...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336
Inventor 吴东平张世理王鹏飞仇志军张卫
Owner FUDAN UNIV